From nobody Wed Nov 27 04:55:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701354889; cv=none; d=zohomail.com; s=zohoarc; b=LcBXTMAyb+0PeOTdw3nAnlaa2TsycC62bTy2f30RI7J6tX+/GjFe0i+d3GSE4ypiwDtVG1v2PDIg2sRq/oMjw9DgvwUxQEraeifG2emJ8cLqtDwKd32B/5Qw2JVfGFJ53wpyVv1g0Pt673XOSlnipUUBx6vtmSgHxfUHqf+jTUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701354889; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CB8r908FrVkxhhiNR7F1JCgcJK/De5QasJhN4UUCdLo=; b=hicrbAVE3LD/+gAWfRRg2Re3PoWF2b4v7XMa4+YXOkVDrqMMu/aAHUJ6P2pS84cDqodtvCxZkeCPbuKcWVJLSj41HX5TQ79zqjQFtZErtes3Ik0JKkAAX45M9/Rx1QtUOjnWLVJzfL60fXmoSGLyXE9SAv0mJ4V/qETfbl82uqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701354889830284.76197786568457; Thu, 30 Nov 2023 06:34:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i6f-0005n9-16; Thu, 30 Nov 2023 09:33:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6a-0005Zs-5H; Thu, 30 Nov 2023 09:33:28 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6Y-0001I2-0p; Thu, 30 Nov 2023 09:33:27 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:33:22 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:33:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354806; x=1732890806; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UIctuJN57ff0cGtb6JQuQGzOnsVqrF/BvG/lcB/CLAU=; b=ikudpG28NQ0aL5uvIg4IVbk4L/60gA/hBg9FC4XM2pCHKXFzWOJKfQiU A36JEIy1CyJ/IaaxOui6LPNLu17LiL8oQa8sWyMgHAN16THmFtxFsCL+9 Z2po8C10Y572Aza7c6u4aUj8dovdLlw8GjsgNnlDvvKFuH2s+EyxF0Qwa sVA5Fly+o8m3nOPH1XG6uBiomCK/ZL/9fgWL59qnh5uFtVESI6+1D1TIR 1mAmnHicXWomN6DAB7co4TDfQJ/iBzudda3L6uLLnDaGR9cvp9BibKcQE tXj2wg3T6dF4m/s4nbGfKNcOfCjwGE/hVQTGP5YjpLOybMQRSS+SsbS1W g==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479531926" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479531926" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730016" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730016" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 18/41] hw/cpu/cluster: Rename CPUClusterState to CPUCluster Date: Thu, 30 Nov 2023 22:41:40 +0800 Message-Id: <20231130144203.2307629-19-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701354890887000003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu To keep the same naming style as cpu-core, rename CPUClusterState to CPUCluster. Signed-off-by: Zhao Liu --- gdbstub/system.c | 2 +- hw/cpu/cluster.c | 8 ++++---- include/hw/arm/armsse.h | 2 +- include/hw/arm/xlnx-versal.h | 4 ++-- include/hw/arm/xlnx-zynqmp.h | 4 ++-- include/hw/cpu/cluster.h | 6 +++--- include/hw/riscv/microchip_pfsoc.h | 4 ++-- include/hw/riscv/sifive_u.h | 4 ++-- 8 files changed, 17 insertions(+), 17 deletions(-) diff --git a/gdbstub/system.c b/gdbstub/system.c index 783ac140b982..1c0b55d3ebe7 100644 --- a/gdbstub/system.c +++ b/gdbstub/system.c @@ -277,7 +277,7 @@ static int find_cpu_clusters(Object *child, void *opaqu= e) { if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { GDBState *s =3D (GDBState *) opaque; - CPUClusterState *cluster =3D CPU_CLUSTER(child); + CPUCluster *cluster =3D CPU_CLUSTER(child); GDBProcess *process; =20 s->processes =3D g_renew(GDBProcess, s->processes, ++s->process_nu= m); diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 61289a840d46..fd978a543e40 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -26,12 +26,12 @@ #include "qapi/error.h" =20 static Property cpu_cluster_properties[] =3D { - DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_UINT32("cluster-id", CPUCluster, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; =20 typedef struct CallbackData { - CPUClusterState *cluster; + CPUCluster *cluster; int cpu_count; } CallbackData; =20 @@ -50,7 +50,7 @@ static int add_cpu_to_cluster(Object *obj, void *opaque) static void cpu_cluster_realize(DeviceState *dev, Error **errp) { /* Iterate through all our CPU children and set their cluster_index */ - CPUClusterState *cluster =3D CPU_CLUSTER(dev); + CPUCluster *cluster =3D CPU_CLUSTER(dev); Object *cluster_obj =3D OBJECT(dev); CallbackData cbdata =3D { .cluster =3D cluster, @@ -87,7 +87,7 @@ static void cpu_cluster_class_init(ObjectClass *klass, vo= id *data) static const TypeInfo cpu_cluster_type_info =3D { .name =3D TYPE_CPU_CLUSTER, .parent =3D TYPE_DEVICE, - .instance_size =3D sizeof(CPUClusterState), + .instance_size =3D sizeof(CPUCluster), .class_init =3D cpu_cluster_class_init, }; =20 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 88b3b759c5a8..886586a3bed4 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -153,7 +153,7 @@ struct ARMSSE { =20 /*< public >*/ ARMv7MState armv7m[SSE_MAX_CPUS]; - CPUClusterState cluster[SSE_MAX_CPUS]; + CPUCluster cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index b24fa64557fd..61bde52b6af5 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -58,7 +58,7 @@ struct Versal { struct { struct { MemoryRegion mr; - CPUClusterState cluster; + CPUCluster cluster; ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; GICv3State gic; } apu; @@ -88,7 +88,7 @@ struct Versal { MemoryRegion mr; MemoryRegion mr_ps_alias; =20 - CPUClusterState cluster; + CPUCluster cluster; ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; } rpu; =20 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 96358d51ebb7..5eea765ea76c 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -98,8 +98,8 @@ struct XlnxZynqMPState { DeviceState parent_obj; =20 /*< public >*/ - CPUClusterState apu_cluster; - CPUClusterState rpu_cluster; + CPUCluster apu_cluster; + CPUCluster rpu_cluster; ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 53fbf36af542..644b87350268 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -55,7 +55,7 @@ */ =20 #define TYPE_CPU_CLUSTER "cpu-cluster" -OBJECT_DECLARE_SIMPLE_TYPE(CPUClusterState, CPU_CLUSTER) +OBJECT_DECLARE_SIMPLE_TYPE(CPUCluster, CPU_CLUSTER) =20 /* * This limit is imposed by TCG, which puts the cluster ID into an @@ -64,13 +64,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(CPUClusterState, CPU_CLUSTER) #define MAX_CLUSTERS 255 =20 /** - * CPUClusterState: + * CPUCluster: * @cluster_id: The cluster ID. This value is for internal use only and sh= ould * not be exposed directly to the user or to the guest. * * State of a CPU cluster. */ -struct CPUClusterState { +struct CPUCluster { /*< private >*/ DeviceState parent_obj; =20 diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index daef086da602..c9ac14e35625 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -38,8 +38,8 @@ typedef struct MicrochipPFSoCState { DeviceState parent_obj; =20 /*< public >*/ - CPUClusterState e_cluster; - CPUClusterState u_cluster; + CPUCluster e_cluster; + CPUCluster u_cluster; RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0696f8594277..fda4a708e960 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -40,8 +40,8 @@ typedef struct SiFiveUSoCState { DeviceState parent_obj; =20 /*< public >*/ - CPUClusterState e_cluster; - CPUClusterState u_cluster; + CPUCluster e_cluster; + CPUCluster u_cluster; RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; --=20 2.34.1