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Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 17/41] hw/cpu/core: Convert cpu-core from general device to topology device Date: Thu, 30 Nov 2023 22:41:39 +0800 Message-Id: <20231130144203.2307629-18-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701355190003000018 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Convert cpu-core to topology device then user could create core level topology from cli and later the cpu-cores could be added into topology tree. In addition, mark the common cpu-core as DEVICE_CATEGORY_CPU_DEF category to indicate it belongs to the basic CPU definition and should be created from cli before board initialization. But since PPC supports CPU hotplug at core granularity, ppc-core should be created after board initialization. Thus, mask the category flag DEVICE_CATEGORY_CPU_DEF for ppc-core. Signed-off-by: Zhao Liu --- hw/cpu/core.c | 19 ++++++++++++++++--- hw/ppc/pnv_core.c | 6 +++++- hw/ppc/ppc_core.c | 5 +++++ hw/ppc/spapr_cpu_core.c | 7 ++++++- include/hw/cpu/core.h | 13 +++++++++++-- include/hw/ppc/pnv_core.h | 1 + include/hw/ppc/spapr_cpu_core.h | 1 + 7 files changed, 45 insertions(+), 7 deletions(-) diff --git a/hw/cpu/core.c b/hw/cpu/core.c index 15546b5b2339..261b15fa8171 100644 --- a/hw/cpu/core.c +++ b/hw/cpu/core.c @@ -27,6 +27,7 @@ static void core_prop_set_nr_threads(Object *obj, Visitor= *v, const char *name, void *opaque, Error **errp) { CPUCore *core =3D CPU_CORE(obj); + CPUTopoState *topo =3D CPU_TOPO(obj); int64_t value; =20 if (!visit_type_int(v, name, &value, errp)) { @@ -34,6 +35,7 @@ static void core_prop_set_nr_threads(Object *obj, Visitor= *v, const char *name, } =20 core->nr_threads =3D value; + topo->max_children =3D core->nr_threads; } =20 static void core_prop_set_plugged_threads(Object *obj, Visitor *v, @@ -53,6 +55,7 @@ static void core_prop_set_plugged_threads(Object *obj, Vi= sitor *v, static void cpu_core_instance_init(Object *obj) { CPUCore *core =3D CPU_CORE(obj); + CPUTopoState *topo =3D CPU_TOPO(obj); =20 /* * Only '-device something-cpu-core,help' can get us there before @@ -64,11 +67,14 @@ static void cpu_core_instance_init(Object *obj) } =20 core->plugged_threads =3D -1; + /* Core's child can only be the thread. */ + topo->child_level =3D CPU_TOPO_THREAD; } =20 static void cpu_core_realize(DeviceState *dev, Error **errp) { CPUCore *core =3D CPU_CORE(dev); + CPUCoreClass *cc =3D CPU_CORE_GET_CLASS(core); =20 if (core->plugged_threads > core->nr_threads) { error_setg(errp, "Plugged threads (plugged-threads: %d) must " @@ -78,25 +84,32 @@ static void cpu_core_realize(DeviceState *dev, Error **= errp) } else if (core->plugged_threads =3D=3D -1) { core->plugged_threads =3D core->nr_threads; } + + cc->parent_realize(dev, errp); } =20 static void cpu_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); + CPUTopoClass *tc =3D CPU_TOPO_CLASS(oc); + CPUCoreClass *cc =3D CPU_CORE_CLASS(oc); =20 - set_bit(DEVICE_CATEGORY_CPU, dc->categories); + set_bit(DEVICE_CATEGORY_CPU_DEF, dc->categories); object_class_property_add(oc, "nr-threads", "int", core_prop_get_nr_th= reads, core_prop_set_nr_threads, NULL, NULL); object_class_property_add(oc, "plugged-threads", "int", NULL, core_prop_set_plugged_threads, NULL, NULL); - dc->realize =3D cpu_core_realize; + device_class_set_parent_realize(dc, cpu_core_realize, &cc->parent_real= ize); + + tc->level =3D CPU_TOPO_CORE; } =20 static const TypeInfo cpu_core_type_info =3D { .name =3D TYPE_CPU_CORE, - .parent =3D TYPE_DEVICE, + .parent =3D TYPE_CPU_TOPO, .abstract =3D true, .class_init =3D cpu_core_class_init, + .class_size =3D sizeof(CPUCoreClass), .instance_size =3D sizeof(CPUCore), .instance_init =3D cpu_core_instance_init, }; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8b75739697d1..315b823e7d38 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -334,6 +334,7 @@ static void pnv_core_unrealize(DeviceState *dev) { PnvCore *pc =3D PNV_CORE(dev); CPUCore *cc =3D CPU_CORE(dev); + PnvCoreClass *pcc =3D PNV_CORE_GET_CLASS(pc); int i; =20 qemu_unregister_reset(pnv_core_reset, pc); @@ -342,6 +343,8 @@ static void pnv_core_unrealize(DeviceState *dev) pnv_core_cpu_unrealize(pc, pc->threads[i]); } g_free(pc->threads); + + pcc->parent_unrealize(dev); } =20 static Property pnv_core_properties[] =3D { @@ -380,11 +383,12 @@ static void pnv_core_class_init(ObjectClass *oc, void= *data) DeviceClass *dc =3D DEVICE_CLASS(oc); PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); =20 - dc->unrealize =3D pnv_core_unrealize; device_class_set_props(dc, pnv_core_properties); dc->user_creatable =3D false; device_class_set_parent_realize(dc, pnv_core_realize, &pcc->parent_realize); + device_class_set_parent_unrealize(dc, pnv_core_unrealize, + &pcc->parent_unrealize); } =20 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ diff --git a/hw/ppc/ppc_core.c b/hw/ppc/ppc_core.c index 3857f3150052..0a700d6a5b42 100644 --- a/hw/ppc/ppc_core.c +++ b/hw/ppc/ppc_core.c @@ -72,6 +72,11 @@ static void powerpc_core_class_init(ObjectClass *oc, voi= d *data) DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCoreClass *ppc_class =3D POWERPC_CORE_CLASS(oc); =20 + /* + * PPC cores support hotplug and must be created after + * qemu_init_board(). + */ + clear_bit(DEVICE_CATEGORY_CPU_DEF, dc->categories); object_class_property_add(oc, "core-id", "int", powerpc_core_prop_get_core_id, powerpc_core_prop_set_core_id, diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 5533a386f350..c965c213ab14 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -235,6 +235,7 @@ static void spapr_delete_vcpu(PowerPCCPU *cpu) static void spapr_cpu_core_unrealize(DeviceState *dev) { SpaprCpuCore *sc =3D SPAPR_CPU_CORE(OBJECT(dev)); + SpaprCpuCoreClass *scc =3D SPAPR_CPU_CORE_GET_CLASS(sc); CPUCore *cc =3D CPU_CORE(dev); int i; =20 @@ -254,6 +255,8 @@ static void spapr_cpu_core_unrealize(DeviceState *dev) } g_free(sc->threads); qemu_unregister_reset(spapr_cpu_core_reset_handler, sc); + + scc->parent_unrealize(dev); } =20 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr, @@ -366,12 +369,14 @@ static void spapr_cpu_core_class_init(ObjectClass *oc= , void *data) DeviceClass *dc =3D DEVICE_CLASS(oc); SpaprCpuCoreClass *scc =3D SPAPR_CPU_CORE_CLASS(oc); =20 - dc->unrealize =3D spapr_cpu_core_unrealize; dc->reset =3D spapr_cpu_core_reset; device_class_set_props(dc, spapr_cpu_core_properties); + dc->hotpluggable =3D true; scc->cpu_type =3D data; device_class_set_parent_realize(dc, spapr_cpu_core_realize, &scc->parent_realize); + device_class_set_parent_unrealize(dc, spapr_cpu_core_unrealize, + &scc->parent_unrealize); } =20 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 87d50151ab01..591240861efb 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -10,15 +10,24 @@ #define HW_CPU_CORE_H =20 #include "hw/qdev-core.h" +#include "hw/core/cpu-topo.h" #include "qom/object.h" =20 #define TYPE_CPU_CORE "cpu-core" =20 -OBJECT_DECLARE_SIMPLE_TYPE(CPUCore, CPU_CORE) +OBJECT_DECLARE_TYPE(CPUCore, CPUCoreClass, CPU_CORE) + +struct CPUCoreClass { + /*< private >*/ + CPUTopoClass parent_class; + + /*< public >*/ + DeviceRealize parent_realize; +}; =20 struct CPUCore { /*< private >*/ - DeviceState parent_obj; + CPUTopoState parent_obj; =20 /*< public >*/ int core_id; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 3b9edf69f9fb..ca04461c8531 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -51,6 +51,7 @@ struct PnvCoreClass { uint64_t xscom_size; =20 DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; }; =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index dabdbd4bcbc9..46cf68fc8859 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -39,6 +39,7 @@ struct SpaprCpuCoreClass { const char *cpu_type; =20 DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; }; =20 const char *spapr_get_cpu_core_type(const char *cpu_type); --=20 2.34.1