From nobody Wed Nov 27 04:41:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701354902; cv=none; d=zohomail.com; s=zohoarc; b=LRiGZyz4q1zsMuUNd1SV0p1Jq/U0KEmMs8lNJt333XLn/jS+1QjS7Sdl9b8O4mPvSMxFhk6hUXUsR63HZblqdvwDScyVVAKSWtSqxIhzN+db7QO3zVHdTeDST0kgcOHbt/63a7r1W1AyW74CrQC2H4/QXzHsLiTLFLe4tXUwYNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701354902; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s0FHlh5NocTVAQ8QPRfvhIq5od/9G9VD8e1wobWtIiw=; b=PC04gJsOF/QgStds1dbAPJqmlCn10WNzONx4GPfU56RjokZJ6IzIBRWHdw7n9RKZPey3UIQt+SRjlClA0H4CMLEfq1R6Ifb9uZvXs3C058RYH82z19nnDBR629I2u7sCGI5WsOZUSXKHOXmRXlwB46EkgWK6zd3sglnPpAqdsVo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701354902923540.3854643214889; Thu, 30 Nov 2023 06:35:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i6L-00047x-D1; Thu, 30 Nov 2023 09:33:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6H-0003yV-Fk; Thu, 30 Nov 2023 09:33:09 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6E-0001EW-Bs; Thu, 30 Nov 2023 09:33:09 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:32:54 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:32:45 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354786; x=1732890786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HQNocPVaV+DgJS+Ld4DvaS6hVw4IdYUlBhgQdcIl19Q=; b=h5Rfb6iQTuIroyQoXUynoGRMPvKTIQtOHQPuV1lnHfqnNQ86qvbjMtXw ldhiGhtkxtHxBk7RT0WFAIAsF95V8DXvVIpVsYCTaLuaWwW4JG5aSEwXX iCtoChT9EzqHXG8masEvnyeck122QSu+kHINuL1ZgupxUjT9qXhDyKKvR y0SeXvLY+BKDTgB4RNgGTWvltWd4ndAb1PV+m7C9owwg6Fx/UD/r0/CS4 Sl8MGNY+WOxBjAfV8udMcjd6RF003bZ5BN3meSQmWpxVn8cJtdvz9AQ6m F7jiMbwhadhBiC/yScfE3xBsp85SJKBeL8y7PzaUn67SjEwa+PgAyTXQy g==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479531806" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479531806" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942729932" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942729932" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 15/41] hw/cpu/core: Allow to configure plugged threads for cpu-core Date: Thu, 30 Nov 2023 22:41:37 +0800 Message-Id: <20231130144203.2307629-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701354904991000002 Content-Type: text/plain; charset="utf-8" From: Zhao Liu When the core abstraction is applied for the architecture support CPU hotplug, the plugged CPUs and unplugged CPUs are distributed among the cores created in the topology tree. Add plugged_threads field to help cpu-core decide to how many CPUs to create. Signed-off-by: Zhao Liu --- hw/cpu/core.c | 33 +++++++++++++++++++++++++++++++++ hw/ppc/pnv_core.c | 6 +++++- hw/ppc/spapr_cpu_core.c | 6 +++++- include/hw/cpu/core.h | 9 +++++++++ include/hw/ppc/pnv_core.h | 2 ++ include/hw/ppc/spapr_cpu_core.h | 2 ++ 6 files changed, 56 insertions(+), 2 deletions(-) diff --git a/hw/cpu/core.c b/hw/cpu/core.c index 7e274d6aebb7..15546b5b2339 100644 --- a/hw/cpu/core.c +++ b/hw/cpu/core.c @@ -36,6 +36,20 @@ static void core_prop_set_nr_threads(Object *obj, Visito= r *v, const char *name, core->nr_threads =3D value; } =20 +static void core_prop_set_plugged_threads(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + CPUCore *core =3D CPU_CORE(obj); + int64_t value; + + if (!visit_type_int(v, name, &value, errp)) { + return; + } + + core->plugged_threads =3D value; +} + static void cpu_core_instance_init(Object *obj) { CPUCore *core =3D CPU_CORE(obj); @@ -48,6 +62,22 @@ static void cpu_core_instance_init(Object *obj) if (current_machine) { core->nr_threads =3D current_machine->smp.threads; } + + core->plugged_threads =3D -1; +} + +static void cpu_core_realize(DeviceState *dev, Error **errp) +{ + CPUCore *core =3D CPU_CORE(dev); + + if (core->plugged_threads > core->nr_threads) { + error_setg(errp, "Plugged threads (plugged-threads: %d) must " + "not be more than max threads (nr-threads: %d)", + core->plugged_threads, core->nr_threads); + return; + } else if (core->plugged_threads =3D=3D -1) { + core->plugged_threads =3D core->nr_threads; + } } =20 static void cpu_core_class_init(ObjectClass *oc, void *data) @@ -57,6 +87,9 @@ static void cpu_core_class_init(ObjectClass *oc, void *da= ta) set_bit(DEVICE_CATEGORY_CPU, dc->categories); object_class_property_add(oc, "nr-threads", "int", core_prop_get_nr_th= reads, core_prop_set_nr_threads, NULL, NULL); + object_class_property_add(oc, "plugged-threads", "int", NULL, + core_prop_set_plugged_threads, NULL, NULL); + dc->realize =3D cpu_core_realize; } =20 static const TypeInfo cpu_core_type_info =3D { diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index a90d1ec92bd8..8b75739697d1 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -276,6 +276,8 @@ static void pnv_core_realize(DeviceState *dev, Error **= errp) =20 assert(pc->chip); =20 + pcc->parent_realize(dev, errp); + pc->threads =3D g_new(PowerPCCPU *, cc->nr_threads); for (i =3D 0; i < cc->nr_threads; i++) { PowerPCCPU *cpu; @@ -376,11 +378,13 @@ static void pnv_core_power10_class_init(ObjectClass *= oc, void *data) static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); + PnvCoreClass *pcc =3D PNV_CORE_CLASS(oc); =20 - dc->realize =3D pnv_core_realize; dc->unrealize =3D pnv_core_unrealize; device_class_set_props(dc, pnv_core_properties); dc->user_creatable =3D false; + device_class_set_parent_realize(dc, pnv_core_realize, + &pcc->parent_realize); } =20 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 7c2ea1424747..5533a386f350 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -331,6 +331,7 @@ static void spapr_cpu_core_realize(DeviceState *dev, Er= ror **errp) (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), TYPE_SPAPR_MACHINE); SpaprCpuCore *sc =3D SPAPR_CPU_CORE(OBJECT(dev)); + SpaprCpuCoreClass *scc =3D SPAPR_CPU_CORE_GET_CLASS(sc); CPUCore *cc =3D CPU_CORE(OBJECT(dev)); int i; =20 @@ -339,6 +340,8 @@ static void spapr_cpu_core_realize(DeviceState *dev, Er= ror **errp) return; } =20 + scc->parent_realize(dev, errp); + qemu_register_reset(spapr_cpu_core_reset_handler, sc); sc->threads =3D g_new0(PowerPCCPU *, cc->nr_threads); for (i =3D 0; i < cc->nr_threads; i++) { @@ -363,11 +366,12 @@ static void spapr_cpu_core_class_init(ObjectClass *oc= , void *data) DeviceClass *dc =3D DEVICE_CLASS(oc); SpaprCpuCoreClass *scc =3D SPAPR_CPU_CORE_CLASS(oc); =20 - dc->realize =3D spapr_cpu_core_realize; dc->unrealize =3D spapr_cpu_core_unrealize; dc->reset =3D spapr_cpu_core_reset; device_class_set_props(dc, spapr_cpu_core_properties); scc->cpu_type =3D data; + device_class_set_parent_realize(dc, spapr_cpu_core_realize, + &scc->parent_realize); } =20 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \ diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 17f117bd5225..87d50151ab01 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -21,7 +21,16 @@ struct CPUCore { DeviceState parent_obj; =20 /*< public >*/ + int core_id; + + /* Maximum number of threads contained in this core. */ int nr_threads; + + /* + * How many threads should be plugged in this core via + * "-device"/"device_add"? + */ + int plugged_threads; }; =20 #endif diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 56c3f6b51f2f..3b9edf69f9fb 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -49,6 +49,8 @@ struct PnvCoreClass { /*< public >*/ const MemoryRegionOps *xscom_ops; uint64_t xscom_size; + + DeviceRealize parent_realize; }; =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index db3e515051ca..dabdbd4bcbc9 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -37,6 +37,8 @@ struct SpaprCpuCoreClass { =20 /*< public >*/ const char *cpu_type; + + DeviceRealize parent_realize; }; =20 const char *spapr_get_cpu_core_type(const char *cpu_type); --=20 2.34.1