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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104912; x=1701709712; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wRdrICC2oih1nk4CtbmyH20uNE3N+a54F03dwas6lTc=; b=mI0KGuxtsAcXZUJ1A1Xzx8Cv4gK0XWGQFRpie9JG0ZJS520KpnApy32T2gjTCobdxe aYQi11BFm3XFNHOSBHFV52wbwX2aJ2LIeyGM+7fai6DWw5eA2dElzERXzv7FjPcgGv89 F3l+0PH+dlOw28rLWc2P/NF7fOuyYNH3v4ppg7GNgKuUynYMjBTsFrrVBIQqfVseNBmx TQhm2WS+2Pb0jI//fczfD8uPrtSpiLBVXzL1yP65Lsj5+5Enps/kOKEKw+fA/+VZzTtP IpNQNzolB+xaZ0inGQT4BT7XTTlKbLlmWa93dRFzsavPlj75v1aQlLCoBv0wf1V1P/2r Ko6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104912; x=1701709712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wRdrICC2oih1nk4CtbmyH20uNE3N+a54F03dwas6lTc=; b=NOPvb/10OY7fwsrXfNlRdyisYql6UIU5me55YfHrRsaUdG2aFwAqgIesXrb0kWo+J0 jaQIWLSJb1bU5RIN0rPS048gtu3Npy1gNmyPLWrXsW9C4vdX9VAAh+0/3B7LnfC/xZ+Q ZMF7HonlRJFUi81rAd6BXzNoh5vthBckoVnjGj+2rszXwuQljTQ3Lp3nu9eJ4OdrETIj 6qZwH+zofqT3DdLVzA1Dh4yoTAUWtRUhd1EFfGQ2G0GNJPrIvSSEa2snaT15O5mYedmB lTZIGSSzjbVZ0Q6npLVWcIjuIzDi8u+MDdmfn5AQWYov8lk2M36EEvbMHuZwskl/YYvu utwA== X-Gm-Message-State: AOJu0YzEuXlka2wEewejdXNzuNFQOiR8mhW+M4bLaJ6YUKZTWuteHGyr VGJT5NsiOQQSXyWKwhgpo+XQqp6zmYuwx2+JbO8= X-Google-Smtp-Source: AGHT+IHlOmK6POWBUtYYRO8kMb41bSVSPf1at9A9WMkGYIRXhYJAeEizzrTUQvvIjSyFqQQ9xh7rCQ== X-Received: by 2002:a05:600c:1d95:b0:407:3b6d:b561 with SMTP id p21-20020a05600c1d9500b004073b6db561mr10255685wms.9.1701104912187; Mon, 27 Nov 2023 09:08:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/13] hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models Date: Mon, 27 Nov 2023 17:08:22 +0000 Message-Id: <20231127170823.589863-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1701104990166000001 Content-Type: text/plain; charset="utf-8" From: Frederic Konrad It seems that the url changed a bit, and it triggers an error. Fix the URL= s so the documentation can be reached again. Signed-off-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20231124143505.1493184-3-fkonrad@amd.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-versal-cframe-reg.h | 2 +- include/hw/misc/xlnx-versal-cfu.h | 2 +- include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 2 +- include/hw/ssi/xlnx-versal-ospi.h | 2 +- hw/dma/xlnx_csu_dma.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/xlnx-versal-cframe-reg.h b/include/hw/misc/xln= x-versal-cframe-reg.h index a14fbd7fe45..0091505246f 100644 --- a/include/hw/misc/xlnx-versal-cframe-reg.h +++ b/include/hw/misc/xlnx-versal-cframe-reg.h @@ -12,7 +12,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/a= m011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-regist= er-reference.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFR= AME_REG-Module */ #ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H #define HW_MISC_XLNX_VERSAL_CFRAME_REG_H diff --git a/include/hw/misc/xlnx-versal-cfu.h b/include/hw/misc/xlnx-versa= l-cfu.h index 86fb8410538..be62bab8c8c 100644 --- a/include/hw/misc/xlnx-versal-cfu.h +++ b/include/hw/misc/xlnx-versal-cfu.h @@ -12,7 +12,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/a= m011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/htmldocs/registers/am012/am012-versal-regist= er-reference.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU= _CSR-Module */ #ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H #define HW_MISC_XLNX_VERSAL_CFU_APB_H diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/x= lnx-versal-pmc-iou-slcr.h index f7d24c93c41..0c4a4fd66d9 100644 --- a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h +++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h @@ -34,7 +34,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/a= m011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/html_docs/registers/am012/am012-versal-regis= ter-reference.html#mod___pmc_iop_slcr.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC= _IOP_SLCR-Module * * QEMU interface: * + sysbus MMIO region 0: MemoryRegion for the device's registers diff --git a/include/hw/ssi/xlnx-versal-ospi.h b/include/hw/ssi/xlnx-versal= -ospi.h index 5d131d351d2..4ac975aa2fd 100644 --- a/include/hw/ssi/xlnx-versal-ospi.h +++ b/include/hw/ssi/xlnx-versal-ospi.h @@ -34,7 +34,7 @@ * https://www.xilinx.com/support/documentation/architecture-manuals/a= m011-versal-acap-trm.pdf * * [2] Versal ACAP Register Reference, - * https://www.xilinx.com/html_docs/registers/am012/am012-versal-regis= ter-reference.html#mod___ospi.html + * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSP= I-Module * * * QEMU interface: diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index e89089821a3..531013f35aa 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -33,7 +33,7 @@ =20 /* * Ref: UG1087 (v1.7) February 8, 2019 - * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascal= e-registers.html + * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascal= e-registers * CSUDMA Module section */ REG32(ADDR, 0x0) --=20 2.34.1