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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id fl8-20020a05600c0b8800b004030e8ff964sm15353216wmb.34.2023.11.27.09.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 09:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701104911; x=1701709711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=r7VN+FUHi4irf+Hlji9rNkb2Vpl4dSI7XsEUkLnRwXY=; b=XKUXt+cZ/EJEc9urUIHlZpL77MT4eP3bdcJxV1go8RlzlQ5EzqREGn3eE+ehjtIL3o RLaEtHmQK+pmpVBdtQaTtXfOqYbptdmnn5DFvuPSN0sW1FszXXa01cO4C2qA1EQWs/Kn g57R1PVDT6/ydrmZg0ah2CSulXebhn0k8psMJ8vfaKvgNRAG8hEpJ0LgR3N3IkpokaFJ TQJ5Q1R9QWetgN3OIAiY2qwPOZRlIVodo2QvStTMUwHLq3Szo8mK1f4XLRX6CGEKPra5 WWa0cLOw3DouQK+vPulMhlOqYtaoi+ngCrgh9l04G91/NfoAZr5gwAdwTlOwaKtC0Bhj TOrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701104911; x=1701709711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7VN+FUHi4irf+Hlji9rNkb2Vpl4dSI7XsEUkLnRwXY=; b=dhi49IksCCmlvQP6VPrPJ6o6HmVpiAMOl5eNTimiz5zwM7iO/upx+qy0/+AjB1ioBd 9f8+fYWWAZFCMdikByhrtA+IWyyrUVrX29nUff3Ku4b44qODyqFwWOTQ6NlDKMwMX7/H KrCpK+R4MsihfRY0f2gH8CYFM83loj9rllvdSyF6VqAV+9ZRsYb6t1oNYPplcCaFutCA Nd8PFT7yQb6mU5wfMZ2457NvCkP8WeN5RVRFnGLQJOEMwE0Mjp9Al2P/uzG7VV5atxwT 10mWS2mAjN7ZnPT//U1UviFCWT25+hFrQ282PQ9sZIFeFC7pcJzL2oAhG6mraPdCm5tl 62fA== X-Gm-Message-State: AOJu0YwFL0U3Bmyd0wF3KCIUbeNV54Z9BFo1bpSzUTYhMcSYDWc8NsvR RdzwibeAA0AqX9UiacJ81YoP+YYieXL5DvVbhfY= X-Google-Smtp-Source: AGHT+IFuj6WVWGl6AUS/UQbvq6SRqgXnU7dR7oz2kGroewS9TL/DH82Djm8sUbpbPMIYUxYHUQlXwg== X-Received: by 2002:a05:651c:48b:b0:2c9:9737:28ab with SMTP id s11-20020a05651c048b00b002c9973728abmr5175016ljc.2.1701104911601; Mon, 27 Nov 2023 09:08:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/13] hw/ssi/xilinx_spips: fix an out of bound access Date: Mon, 27 Nov 2023 17:08:21 +0000 Message-Id: <20231127170823.589863-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127170823.589863-1-peter.maydell@linaro.org> References: <20231127170823.589863-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1701105114781000004 Content-Type: text/plain; charset="utf-8" From: Frederic Konrad The spips, qspips, and zynqmp-qspips share the same realize function (xilinx_spips_realize) and initialize their io memory region with different mmio_ops passed through the class. The size of the memory region is set to the largest area (0x200 bytes for zynqmp-qspips) thus it is possible to wri= te out of s->regs[addr] in xilinx_spips_write for spips and qspips. This fixes that wrong behavior. Reviewed-by: Luc Michel Signed-off-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20231124143505.1493184-2-fkonrad@amd.com Signed-off-by: Peter Maydell --- include/hw/ssi/xilinx_spips.h | 3 +++ hw/ssi/xilinx_spips.c | 7 ++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 1386d5ac8fe..7a754bf67a2 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -33,7 +33,9 @@ =20 typedef struct XilinxSPIPS XilinxSPIPS; =20 +/* For SPIPS, QSPIPS. */ #define XLNX_SPIPS_R_MAX (0x100 / 4) +/* For ZYNQMP_QSPIPS. */ #define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) =20 /* Bite off 4k chunks at a time */ @@ -125,6 +127,7 @@ struct XilinxSPIPSClass { SysBusDeviceClass parent_class; =20 const MemoryRegionOps *reg_ops; + uint64_t reg_size; =20 uint32_t rx_fifo_size; uint32_t tx_fifo_size; diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a3955c6c50c..0bdfad7e2e5 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -973,6 +973,8 @@ static void xilinx_spips_write(void *opaque, hwaddr add= r, =20 DB_PRINT_L(0, "addr=3D" HWADDR_FMT_plx " =3D %x\n", addr, (unsigned)va= lue); addr >>=3D 2; + assert(addr < XLNX_SPIPS_R_MAX); + switch (addr) { case R_CONFIG: mask =3D ~(R_CONFIG_RSVD | MAN_START_COM); @@ -1299,7 +1301,7 @@ static void xilinx_spips_realize(DeviceState *dev, Er= ror **errp) } =20 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, - "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); + "spi", xsc->reg_size); sysbus_init_mmio(sbd, &s->iomem); =20 s->irqline =3D -1; @@ -1435,6 +1437,7 @@ static void xilinx_qspips_class_init(ObjectClass *kla= ss, void * data) =20 dc->realize =3D xilinx_qspips_realize; xsc->reg_ops =3D &qspips_ops; + xsc->reg_size =3D XLNX_SPIPS_R_MAX * 4; xsc->rx_fifo_size =3D RXFF_A_Q; xsc->tx_fifo_size =3D TXFF_A_Q; } @@ -1450,6 +1453,7 @@ static void xilinx_spips_class_init(ObjectClass *klas= s, void *data) dc->vmsd =3D &vmstate_xilinx_spips; =20 xsc->reg_ops =3D &spips_ops; + xsc->reg_size =3D XLNX_SPIPS_R_MAX * 4; xsc->rx_fifo_size =3D RXFF_A; xsc->tx_fifo_size =3D TXFF_A; } @@ -1464,6 +1468,7 @@ static void xlnx_zynqmp_qspips_class_init(ObjectClass= *klass, void * data) dc->vmsd =3D &vmstate_xlnx_zynqmp_qspips; device_class_set_props(dc, xilinx_zynqmp_qspips_properties); xsc->reg_ops =3D &xlnx_zynqmp_qspips_ops; + xsc->reg_size =3D XLNX_ZYNQMP_SPIPS_R_MAX * 4; xsc->rx_fifo_size =3D RXFF_A_Q; xsc->tx_fifo_size =3D TXFF_A_Q; } --=20 2.34.1