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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id q15-20020a63e94f000000b00578b40a4903sm7618323pgj.22.2023.11.27.03.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 03:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701085104; x=1701689904; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tmRYxbcrT44VCzWYmzhlhuQ/rR3RdlkH5p1bUIHDcZI=; b=ce+6E2/PlMKeV6iigaewFB0/Q1zaD8XXkPbAPkA4hsJ3ebvEFg6csHdS+dSbxrKa+O dnr+kIbgS6ym9a25LijO5w24SYVQVpRtGqWgebedBlZK9HR0q+lv/UCZk7isGuBqZFWj L4qjOQjW+pIdRiBFEIusAEhG5gcP57duEgPVU61tctiRp5XAFiBuOjpEE6WK0vKrsX3v PzVUaEGWm0eE/yimWkT4haSDt4aRbQQobvcV9yodf7Zib+N958faHvOw1fAjKhy/Q0jb WI9pUJf7uPcAUt20W1fNSQRvkr+VK8SGgxwWcyybX8ghaBQW9YCbTI/y3dYRenEtyCuN Zdcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701085104; x=1701689904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tmRYxbcrT44VCzWYmzhlhuQ/rR3RdlkH5p1bUIHDcZI=; b=SQcgx9tKGAG+1xI2GtOcTWrBItq64iG/v52lmm1pxQogI8xc4cpTVE0wr5l/OgyU4P 7HUKgfE8sS40pYshQoBnuZ8yFck6oQ46jeVNjqn+8SWuatpkvw83j53h0lVnW97acO/m +Gdzutz7tzxmixV/U1MsXypzBmxZNVfyy9uRHMmZwmlIlnq2KuQOPOAtHIoVesT7IpRc BF2812LtmLgK3/NlyYIEraKvTxSRSX9aOwk7b6GsTfHPWlIfMFtL7TadYqZRK4zHGIYL xe5cHIkhvYDvzMjj29GtTUBuJQ+MK0091AW24kzUMYTTKmfRHtQdK2n1qpyH0TLxeqY8 IGGw== X-Gm-Message-State: AOJu0Yy2Kn9C86H56YBSftCEIr9ivZlXLyxoChZAGUVG+ugfKfzgUbUK QZvP2j4DCg7y3LaqJnvP2TIPwdCiQcZb6dG2yuA= X-Google-Smtp-Source: AGHT+IEdDLn4fANEtxaGtgSTCKtJtfHcr1BHcZmtfwltJCP0wiZnlQzWVfINsjoTTOckZUmkWoaYPA== X-Received: by 2002:a05:6808:f90:b0:3a9:cfb5:462a with SMTP id o16-20020a0568080f9000b003a9cfb5462amr12354975oiw.36.1701085104231; Mon, 27 Nov 2023 03:38:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v2 8/8] target/riscv: add rva22s64 cpu Date: Mon, 27 Nov 2023 08:37:52 -0300 Message-ID: <20231127113752.1290265-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231127113752.1290265-1-dbarboza@ventanamicro.com> References: <20231127113752.1290265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1701085196129000002 Content-Type: text/plain; charset="utf-8" Add a new profile CPU 'rva22s64' to work as an alias of -cpu rv64i,rva22s64 Like the existing rva22u64 CPU already does with the RVA22U64 profile. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 12fe78fc52..9219c2fcc3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") +#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fa056fb45f..99bdb96335 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1624,6 +1624,13 @@ static void rva22u64_profile_cpu_init(Object *obj) =20 RVA22U64.enabled =3D true; } + +static void rva22s64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA22S64.enabled =3D true; +} #endif =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -1968,6 +1975,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), #endif }; =20 --=20 2.41.0