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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id q15-20020a63e94f000000b00578b40a4903sm7618323pgj.22.2023.11.27.03.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 03:38:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701085084; x=1701689884; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dGNqscTm0j47pNh5vB1J02Wn8NgcJ09lbo8OaJQCkt0=; b=okmEcH04fRHdKvmeVgga+gfgEMNxdoPI+kpEcfR38/CpS75Xwk7xz8/efhZxrWOvxr yGwkLizcqAHCo1IJysQZSQ/jSqsKjui5JD7t+Xk2mbr5QV4Ve5USCbtiL5gGKtCvuWkw wlpj8VjPGR5iKeRr7PRGIPQgk2A8ffClOhhtlX0woXHBNTDv43jjNrBK2uCvNbGzdDld LKFmCOolpzcEhAe9gl9HgxnfEH72XBB5cinp9UC5L9qOGeT4FQWgRTeWeyQ+uFLPsYj4 O3xDC7q8GqnbaW+tjusYqTqLSnEopfYz2aKTyg3o7KsqvCFMGz8cpC9ShJdOsxuvmAm0 1nRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701085084; x=1701689884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGNqscTm0j47pNh5vB1J02Wn8NgcJ09lbo8OaJQCkt0=; b=xFwDvk5FhqAR1ukem9xPFjwNEl0BMKdHyUf7egIO0Z/XfjxTVHb+A4f1npWRxdpREN YWgnQk3jXmI1Gmfy/jG1AqhX2WbJ4JR7zZ5sKblW7sRrkvRaXLX9Gf5A19KYvtJR6lY8 iMf1YLT8DD2h2I4lB+mAc7LOB3Qb6LVg7PPyIJ0NNbY/8qW8ouB2yKXh7YRjGAM4Y9M8 iUju6HUD0G8//TvJ5EOiqbvsAzNKGhjwTgu8piM97TE12/+poIzUi+lxRWcjFFWKSgSw i16A8+Mbzuphecj6rQTRKF4amsU5Tl6EtRC8MW+vrGP9y78D+eyKMqSAS25bMtCD89/g 2Ysw== X-Gm-Message-State: AOJu0YzqLzqsQsfRlTXvwu71rMAA7nBD/cq3YyW11MVEz6EGXXZR0SbK jh0qmamKJaVV/IktNL4/2hnMe5wvhPuc20d8/Jo= X-Google-Smtp-Source: AGHT+IFO4nub4CFKBoScddwqgyPE6APX3r3t2ZJRaunzsq6VUBtg+zRYPgER0EHbQVKKLXXtv0mLkg== X-Received: by 2002:a9d:6c90:0:b0:6ce:2789:7195 with SMTP id c16-20020a9d6c90000000b006ce27897195mr11117799otr.31.1701085084503; Mon, 27 Nov 2023 03:38:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v2 2/8] target/riscv: add priv ver restriction to profiles Date: Mon, 27 Nov 2023 08:37:46 -0300 Message-ID: <20231127113752.1290265-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231127113752.1290265-1-dbarboza@ventanamicro.com> References: <20231127113752.1290265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1701085171504000005 Content-Type: text/plain; charset="utf-8" Some profiles, like RVA22S64, has a priv_spec requirement. Make this requirement explicit for all profiles. We'll validate this requirement finalize() time and, in case the user chooses an incompatible priv_spec while activating a profile, a warning will be shown. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 59b131c1fc..29a9f77702 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1537,6 +1537,7 @@ Property riscv_cpu_options[] =3D { static RISCVCPUProfile RVA22U64 =3D { .name =3D "rva22u64", .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, .ext_offsets =3D { CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5ff629650d..1f34eda1e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,10 +81,12 @@ typedef struct riscv_cpu_profile { uint32_t misa_ext; bool enabled; bool user_set; + int priv_spec; const int32_t ext_offsets[]; } RISCVCPUProfile; =20 #define RISCV_PROFILE_EXT_LIST_END -1 +#define RISCV_PROFILE_ATTR_UNUSED -1 =20 extern RISCVCPUProfile *riscv_profiles[]; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e395e2449e..4d25fc43d2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -74,6 +74,20 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint= 32_t bit, } } =20 +static const char *cpu_priv_ver_to_str(int priv_ver) +{ + switch (priv_ver) { + case PRIV_VERSION_1_10_0: + return "v1.10.0"; + case PRIV_VERSION_1_11_0: + return "v1.11.0"; + case PRIV_VERSION_1_12_0: + return "v1.12.0"; + } + + g_assert_not_reached(); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -755,11 +769,24 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_profile(RISCVCPU *cpu, RISCVCPUProfile *profile) { + CPURISCVState *env =3D &cpu->env; const char *warn_msg =3D "Profile %s mandates disabled extension %s"; bool send_warn =3D profile->user_set && profile->enabled; bool profile_impl =3D true; int i; =20 + if (profile->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED && + profile->priv_spec !=3D env->priv_ver) { + profile_impl =3D false; + + if (send_warn) { + warn_report("Profile %s requires priv spec %s, " + "but priv ver %s was set", profile->name, + cpu_priv_ver_to_str(profile->priv_spec), + cpu_priv_ver_to_str(env->priv_ver)); + } + } + for (i =3D 0; misa_bits[i] !=3D 0; i++) { uint32_t bit =3D misa_bits[i]; =20 @@ -1048,6 +1075,10 @@ static void cpu_set_profile(Object *obj, Visitor *v,= const char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + if (profile->enabled) { + cpu->env.priv_ver =3D profile->priv_spec; + } + for (i =3D 0; misa_bits[i] !=3D 0; i++) { uint32_t bit =3D misa_bits[i]; =20 --=20 2.41.0