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([152.250.131.119]) by smtp.gmail.com with ESMTPSA id t24-20020a1709028c9800b001c59f23a3fesm3548267plo.251.2023.11.24.12.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 12:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700857460; x=1701462260; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nZQGq1vpi0VyjQUL40qJ/4evWzPTAviR68lj3o0swgo=; b=TUZ+Memp3ZOPrlp9R40PMTUNkJyjCeT3uc5wdAbtmTUSBrMaDCQzTbProP3b+ElJRc +hQc3CDAT8NZQ6CGIwSrRbKDOQ8PFG75lqUjZrZfekldqi6MIPl5/8NSnaKrcRg0HTlP LMzJO/+2UJGQkwI3C23anF1RuSI313PjYQi4olP/MNrWDsZr13RwZda+/5rs99YKKCWj cx8L1/ytxsvJRxuCEaYFRnjxdZw4MQQu+k0nJ6VcE153D04zxCRuuSZ+obnVrINgwKJA jimuwKO3kKCUyiU42PAarhNhSUdhuxWzmSNtAwJumgDDs73yD6fT1PAm4sAtg6qURnlu f8TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700857460; x=1701462260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nZQGq1vpi0VyjQUL40qJ/4evWzPTAviR68lj3o0swgo=; b=mwr3KlcAvh0w+0D2wcFUwyCn3LJoVBBcw2UyMC5Nk0+mBQX8boGgUE1AVDyOncv+vf zjCuAA3ImLm0f9itG8pwwV0d4aP//0m5W09EGfXO4H4YbDjGJRgtbENuSbh7ZO+2ZEfq RWbJl16Ow9lfCWSqQ4G+sJuMTlwXaYaAgll6egBtkLeIOG/x1aHPOtgn7O9acCevM5sg jk8lHppDPMhOnJ/g6o6tSu9mHeN9WW7oTcXDEg1U7v0SfiorjVzk/uxfTPOX39YePdzX Sh8JZkVMjQa7IvMYK6qmLvTs/fYR9GIQAy6AGqT/ehthvQK0x0YAbF0yNIljm/s0w8fF 7Jpg== X-Gm-Message-State: AOJu0YxX4Yu/0SLrKSL44r1ICkexhcMYpiVo8QfDK9Dd+USbBWWKcJOs OQYBDpAoef0kBGVPpOywspXcglwbl4AESA+b97A= X-Google-Smtp-Source: AGHT+IGD94p1XkylWnzOvFBoRl80BlA+NQS2DBDY3tVhn5+CXMGwBBH6yohmKNWiX2736br2N5BZTw== X-Received: by 2002:a17:902:e88d:b0:1cc:6dd4:594d with SMTP id w13-20020a170902e88d00b001cc6dd4594dmr4665814plg.42.1700857460414; Fri, 24 Nov 2023 12:24:20 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v12 06/18] target/riscv/tcg: add 'zic64b' support Date: Fri, 24 Nov 2023 17:23:41 -0300 Message-ID: <20231124202353.1187814-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124202353.1187814-1-dbarboza@ventanamicro.com> References: <20231124202353.1187814-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700857625633100001 Content-Type: text/plain; charset="utf-8" zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64 bytes cache blocks. To make the upcoming RVA22U64 implementation complete, we'll zic64b as a 'named feature', not a regular extension. This means that: - it won't be exposed to users; - it won't be written in riscv,isa. This will be extended to other named extensions in the future, so we're creating some common boilerplate for them as well. zic64b is default to 'true' since we're already using 64 bytes blocks. If any cache block size (cbo{m,p,z}_blocksize) is changed to something different than 64, zic64b is set to 'false'. Our profile implementation will then be able to check the current state of zic64b and take the appropriate action (e.g. throw a warning). [1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles= .pdf Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 26 ++++++++++++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 40c64581ec..8841052290 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1444,6 +1444,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { + MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), + + DEFINE_PROP_END_OF_LIST(), +}; + /* Deprecated entries marked for future removal */ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] =3D { MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..5fb4ca2324 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -767,6 +767,7 @@ typedef struct RISCVCPUMultiExtConfig { extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; extern Property riscv_cpu_options[]; =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index bd2ff87cc8..90f18eb601 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -116,6 +116,7 @@ struct RISCVCPUConfig { bool ext_smepmp; bool rvv_ta_all_1s; bool rvv_ma_all_1s; + bool zic64b; =20 uint32_t mvendorid; uint64_t marchid; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index aee98db6f8..3319ba8e4e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return true; + } + } + + return false; +} + static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -123,6 +136,10 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState = *env, return; } =20 + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + return; + } + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); =20 if (env->priv_ver < ext_priv_ver) { @@ -293,6 +310,13 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_update_named_features(RISCVCPU *cpu) +{ + cpu->cfg.zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && + cpu->cfg.cbop_blocksize =3D=3D 64 && + cpu->cfg.cboz_blocksize =3D=3D 64; +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -657,6 +681,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) return; } =20 + riscv_cpu_update_named_features(cpu); + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.41.0