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([152.250.131.119]) by smtp.gmail.com with ESMTPSA id t24-20020a1709028c9800b001c59f23a3fesm3548267plo.251.2023.11.24.12.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 12:24:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700857484; x=1701462284; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cmianI1JgQMdz0IgEKTk7UjMG4HIUynTyTAk4C8O4NY=; b=lFJJGTkpzqKUgd/DePJqt8tZgxxfE9EDqFs24DqqX10zMvbl/1qZvsqouEzgPABLzW 7LRNrMiZEBUMugTLst6w/WlKq32AooOgIxUH35l56KX0SdpjfwqmfMKlZQLf8MU912p/ culmk2POxP3Bdn63cabDS3oC0NBkIkPa2p2hPOYDeYuvKPxzzpRlLrOQxi5e241E+aH/ Xr2OO2TUk4MI9ousOq+0aegvxeVlrkyCrWx37Outu4VKZrFG4cWy5NmGix8qo6cHWR0C 3SdX+2BLfdM1cDB/VW89K5915BpLwENkTvFVON1SQcfqE3pTy1UvBfFEk5zg5Rnp+Iat 1zxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700857484; x=1701462284; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cmianI1JgQMdz0IgEKTk7UjMG4HIUynTyTAk4C8O4NY=; b=kIWfDa0prGtoNPzL/2ThKcMsk1FGisxvJAL8jIlOm8b5ThTI/qCGyZIHWiA4BpSalL 5oW4xJXGyximi9jfqhR1//THZTjJcirzZWp7FVoxkME9N3Yuc3b1jvXbOcV/EwiK8fSb L4fAb92ynAiIFGR7aLs16VSjt/nWAcr8XLtT3QWCX0KeX+l4SOKS6CRqJD2uhjgD/MRV PeOFAKFDHQ+q5nm6OuUTJOtQSGr3dq2G7tEwAf4oLJRAAkTO9wi6prYIVmwaSINRejFs jLUDnndKTBELsFHgWXqIt9f/FM/nN71P0IatROQ9Ol+ntUD1LLlT/1hbLJZh1RusKno9 bzPA== X-Gm-Message-State: AOJu0Yww14d3S4WoLrwxSLj9dg1sktzCAzl1xAKXiIb6yarfm0MI7DpR 0w0ZvcqdMtboKMs3PFWIvQ1elGBqdgJpVSLwQPc= X-Google-Smtp-Source: AGHT+IFBWXLgbRosSamzLPqY9E8OZkdDdxtrDNxrDJekcUq0muGF2pqVSyGwWHCu208cV0Ko+3MVfA== X-Received: by 2002:a17:903:2345:b0:1cf:b357:c8f4 with SMTP id c5-20020a170903234500b001cfb357c8f4mr100691plh.55.1700857484763; Fri, 24 Nov 2023 12:24:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v12 14/18] target/riscv/tcg: add hash table insert helpers Date: Fri, 24 Nov 2023 17:23:49 -0300 Message-ID: <20231124202353.1187814-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124202353.1187814-1-dbarboza@ventanamicro.com> References: <20231124202353.1187814-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700857562327100001 Content-Type: text/plain; charset="utf-8" Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f2e0ce0f3d..01d2cc9f94 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,18 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +{ + g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), + (gpointer)value); +} + +static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +{ + g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), + (gpointer)value); +} + static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled) { @@ -817,9 +829,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, return; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(misa_bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(misa_bit, value); =20 prev_val =3D env->misa_ext & misa_bit; =20 @@ -956,9 +966,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, continue; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } =20 @@ -973,9 +981,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset), - (gpointer)profile->enabled); + cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -1038,9 +1044,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, multi_ext_cfg->name, lower); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); + cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); =20 prev_val =3D isa_ext_is_enabled(cpu, multi_ext_cfg->offset); =20 --=20 2.41.0