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([152.250.131.119]) by smtp.gmail.com with ESMTPSA id t24-20020a1709028c9800b001c59f23a3fesm3548267plo.251.2023.11.24.12.24.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 12:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700857481; x=1701462281; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YPXXV9bkY2OSq9AnfDFrJZbtoSfi0+GO4F9KAkwaxAQ=; b=NyCiGnpnNCthmHL4D0s2j8pR9kvP6peIIATCHhUzKwi0Dgc2HpFDKj31Far3FtYs1B OKqQ8BfYZu2V4quwP/T5+tUmZq9zwSR1YH2uRQW5OkLfxPZcMAjGCVJt/QHrvJwtxDs+ kgOERP++BzNwz+/4uAeNs4Yea/2y+qHMexzTURMdGaz9yYcxQpagmWsqccx1BIwesXD9 ZUyWhkEM2W5LhHe8UTgtn559K7NTIRlAa+In/uMyIPKAGBAq240QhLHTmE0bx0KBf52y OZSh2sj9L4VDdF/2OLjz1gPpU11AKPR+Hs4+Q8UO7WuKW+Vr3j0JnNSsVUJz9lxzO+DP qzEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700857481; x=1701462281; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YPXXV9bkY2OSq9AnfDFrJZbtoSfi0+GO4F9KAkwaxAQ=; b=N4fwPX/CfARCAKr2tDvsj6e8iSfN9u7GNZCGKuNjp1aftXjTZH3PDn1XeKP0T9jq8r ShgNPUIRaHcHdp9FCPVrvRyvdqPUTXvSmFjmNram3E7CmOQg2wY2+131QnzszUMTaHFi V25uCN7LzM76EfO+GJ/Ec33tr/lBYu8a4595xwNny5OJDn5udnu/uajxQV2IxNb2jS+p Q5MkPeww0WIvs2r0On8044OkpSYOivzAbWVMow2kdp2afpDAwNL6lcl52t7shXGQJ9+3 Qah3SdCX/ZUFBYKXJgOrqtCyhRfvZZZV/g1tdvKkNo586lXeg41FM+JXtxz14WNavKsA WuCw== X-Gm-Message-State: AOJu0YzAD+g6EpKFLuktgbv5Qi0XGTZaS6lseJBbWViIQUBuohLLLw3Q GmxtIyu3v1sX451u07dlVUfIOBxdCNKMN6hTrfY= X-Google-Smtp-Source: AGHT+IG5Q3qNUC//xfLEYNtr9rZKbeBxVCVBeK76+ueT4iIQf6YlMf/HWXsZ9EchRsGmGB6yz25tCg== X-Received: by 2002:a17:902:ea84:b0:1cf:5c99:75f8 with SMTP id x4-20020a170902ea8400b001cf5c9975f8mr4446574plb.65.1700857481721; Fri, 24 Nov 2023 12:24:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v12 13/18] target/riscv/tcg: handle profile MISA bits Date: Fri, 24 Nov 2023 17:23:48 -0300 Message-ID: <20231124202353.1187814-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124202353.1187814-1-dbarboza@ventanamicro.com> References: <20231124202353.1187814-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700857568427100003 Content-Type: text/plain; charset="utf-8" The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting profile MISA bits, one can use the rv64i CPU to boot Linux using the following options: -cpu rv64i,rva22u64=3Dtrue,rv39=3Dtrue,s=3Dtrue,zifencei=3Dtrue In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are mandatory), is implemented, rv64i will be able to boot Linux loading rva22s64 and no additional flags. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f8c35ba060..f2e0ce0f3d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -941,6 +941,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, c= onst char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit =3D=3D RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { ext_offset =3D profile->ext_offsets[i]; =20 --=20 2.41.0