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([152.250.131.119]) by smtp.gmail.com with ESMTPSA id t24-20020a1709028c9800b001c59f23a3fesm3548267plo.251.2023.11.24.12.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 12:24:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700857478; x=1701462278; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xENcAmu8U/oRjVCoIGnLFQAM52fQXkmQzw7GARR4+1I=; b=dyQar/1YTabuJPMU1MbtfKSlVmgh/Wr0AlbifzEUdNOMG+8QMYI6qIremgfRoLmnFO +bYsZf8a9NOVwG/w696I7UYBYjCFxpknEOOcgV7sfJFgiF21PRMUpHPNvhUIlZe5JoR6 /QGtRm5vg2p2hh1OKyJ7Q5PRTn6pD6i8RD4bH08emiew9WIlp9C0VTRjLrcLj6L5u+hN 2fzhylt8r2pM9n5jFqZNxXQbJkVFUBlrz0UyQfpxkVUGXpd/oHa1Wz5+NXQkbrZ2hX3e 1QD1nqqS8l/AmYlBn65ms0mIQ9yoVkpaTIEhFJ97EEPYCQg5EJ4IaDY793w/6bvnzazj 4lCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700857478; x=1701462278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xENcAmu8U/oRjVCoIGnLFQAM52fQXkmQzw7GARR4+1I=; b=Er+3jXxOWkcS62ds96qq7WAvZjiwoF1H03853unEf7m6OvjFvE+yceX70Zfzpb5kVh bVXHCBHLA4gWtCAOGB4kkcLg+GiSz6mJtfYLXLsfjxWzRS7OmmUJmuK3c8d/qnOWpvhT MesnpL+VdrsyD0HAiW7VH7DUDYyDl+4lFO9mfBHI29OOIii97IOVFE8MUPio64dj9KbC XSBsDuW1Rz+vO7sVGsa40orz0iGWLDPYy5Nq7XJTrSYZRCdjeCr5c/qx42HLZYJknOOQ E8ajohldSrc2Sy+NUVDsI4uQI71fv+JT3YYNX1fZEObrKztPi8KlXdtytQL/Hfv8Dd2n 1KwQ== X-Gm-Message-State: AOJu0YzQaUex+JCDND/vDFQdZSEY1vkOI8js4RJoturEURb69FqAUJZ3 4zWqTIgV2ArHilwQEhJE+8920iwNV6ZKVP7MoQ0= X-Google-Smtp-Source: AGHT+IHABed7BtJP4PKkG0gaRbz4PYEHujl9AaFpJ0n2/l2XSB3lAxubg68cVUBgAqLPOVwVAmgSGA== X-Received: by 2002:a17:903:2308:b0:1ce:6312:5373 with SMTP id d8-20020a170903230800b001ce63125373mr4486121plh.0.1700857478659; Fri, 24 Nov 2023 12:24:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v12 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Fri, 24 Nov 2023 17:23:47 -0300 Message-ID: <20231124202353.1187814-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124202353.1187814-1-dbarboza@ventanamicro.com> References: <20231124202353.1187814-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700857609386100003 Content-Type: text/plain; charset="utf-8" We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2affc1f771..f8c35ba060 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env =3D &cpu->env; + + if (enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -828,13 +842,9 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, */ env->priv_ver =3D PRIV_VERSION_1_12_0; } - - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } =20 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -878,7 +888,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -899,13 +908,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |=3D bit; - env->misa_ext_mask |=3D bit; - } else { - env->misa_ext &=3D ~bit; - env->misa_ext_mask &=3D ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } } --=20 2.41.0