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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=npiggin@gmail.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1700808137265100001 Content-Type: text/plain; charset="utf-8" One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 2 + include/hw/ppc/pnv_chiptod.h | 4 ++ target/ppc/cpu.h | 7 ++ hw/ppc/pnv.c | 15 ++++ hw/ppc/pnv_chiptod.c | 132 +++++++++++++++++++++++++++++++++++ 5 files changed, 160 insertions(+) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7e5fef7c43..005048d207 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -28,6 +28,7 @@ =20 #define TYPE_PNV_CHIP "pnv-chip" =20 +typedef struct PnvCore PnvCore; typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; typedef struct Pnv9Chip Pnv9Chip; @@ -56,6 +57,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) =20 +PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); =20 typedef struct PnvPHB PnvPHB; diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h index f873901ee7..b021ec81fe 100644 --- a/include/hw/ppc/pnv_chiptod.h +++ b/include/hw/ppc/pnv_chiptod.h @@ -25,6 +25,8 @@ enum tod_state { tod_stopped =3D 1, }; =20 +typedef struct PnvCore PnvCore; + struct PnvChipTOD { DeviceState xd; =20 @@ -36,12 +38,14 @@ struct PnvChipTOD { enum tod_state tod_state; uint64_t tod_error; uint64_t pss_mss_ctrl_reg; + PnvCore *slave_pc_target; }; =20 struct PnvChipTODClass { DeviceClass parent_class; =20 void (*broadcast_ttype)(PnvChipTOD *sender, uint32_t trigger); + PnvCore *(*tx_ttype_target)(PnvChipTOD *chiptod, uint64_t val); =20 int xscom_size; const MemoryRegionOps *xscom_ops; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 848e583c2d..d7cfdeb3b6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1258,6 +1258,13 @@ struct CPUArchState { uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 + +#if defined(TARGET_PPC64) + /* PowerNV chiptod / timebase facility state. */ + /* Would be nice to put these into PnvCore */ + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ + int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ +#endif #endif =20 /* Other registers */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 546266ae3d..f42e70d716 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2065,6 +2065,21 @@ static void pnv_chip_class_init(ObjectClass *klass, = void *data) dc->desc =3D "PowerNV Chip"; } =20 +PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) +{ + int i; + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pc =3D chip->cores[i]; + CPUCore *cc =3D CPU_CORE(pc); + + if (cc->core_id =3D=3D core_id) { + return pc; + } + } + return NULL; +} + PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) { int i, j; diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c index 88d285a332..c494daac7f 100644 --- a/hw/ppc/pnv_chiptod.c +++ b/hw/ppc/pnv_chiptod.c @@ -210,6 +210,79 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD= *sender, } } =20 +static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip, + uint32_t xscom_base) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + int i; + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pc =3D chip->cores[i]; + CPUCore *cc =3D CPU_CORE(pc); + int core_hwid =3D cc->core_id; + + if (pcc->xscom_core_base(chip, core_hwid) =3D=3D xscom_base) { + return pc; + } + } + return NULL; +} + +static PnvCore *chiptod_power9_tx_ttype_target(PnvChipTOD *chiptod, + uint64_t val) +{ + /* + * skiboot uses Core ID for P9, though SCOM should work too. + */ + if (val & PPC_BIT(35)) { /* SCOM addressing */ + uint32_t addr =3D val >> 32; + uint32_t reg =3D addr & 0xfff; + + if (reg !=3D PC_TOD) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " + "unimplemented slave register 0x%" PRIx32 "\n", = reg); + return NULL; + } + + return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xff= f); + + } else { /* Core ID addressing */ + uint32_t core_id =3D GETFIELD(TOD_TX_TTYPE_PIB_SLAVE_ADDR, val) & = 0x1f; + return pnv_chip_find_core(chiptod->chip, core_id); + } +} + +static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod, + uint64_t val) +{ + /* + * skiboot uses SCOM for P10 because Core ID was unable to be made to + * work correctly. For this reason only SCOM addressing is implemented. + */ + if (val & PPC_BIT(35)) { /* SCOM addressing */ + uint32_t addr =3D val >> 32; + uint32_t reg =3D addr & 0xfff; + + if (reg !=3D PC_TOD) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " + "unimplemented slave register 0x%" PRIx32 "\n", = reg); + return NULL; + } + + /* + * This may not deal with P10 big-core addressing at the moment. + * The big-core code in skiboot syncs small cores, but it targets + * the even PIR (first small-core) when syncing second small-core. + */ + return pnv_chip_get_core_by_xscom_base(chiptod->chip, addr & ~0xff= f); + + } else { /* Core ID addressing */ + qemu_log_mask(LOG_UNIMP, "pnv_chiptod: TX TTYPE Core ID " + "addressing is not implemented for POWER10\n"); + return NULL; + } +} + static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size, bool is_power9) @@ -232,6 +305,22 @@ static void pnv_chiptod_xscom_write(void *opaque, hwad= dr addr, chiptod->pss_mss_ctrl_reg =3D val & PPC_BITMASK(0, 31); break; =20 + case TOD_TX_TTYPE_CTRL_REG: + /* + * This register sets the target of the TOD value transfer initiat= ed + * by TOD_MOVE_TOD_TO_TB. The TOD is able to send the address to + * any target register, though in practice only the PC TOD register + * should be used. ChipTOD has a "SCOM addressing" mode which fully + * specifies the SCOM address, and a core-ID mode which uses the + * core ID to target the PC TOD for a given core. + */ + chiptod->slave_pc_target =3D pctc->tx_ttype_target(chiptod, val); + if (!chiptod->slave_pc_target) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64 + " invalid slave address\n", val); + } + break; case TOD_ERROR_REG: chiptod->tod_error &=3D ~val; break; @@ -257,6 +346,47 @@ static void pnv_chiptod_xscom_write(void *opaque, hwad= dr addr, } } break; + + case TOD_MOVE_TOD_TO_TB_REG: + /* + * XXX: it should be a cleaner model to have this drive a SCOM + * transaction to the target address, and implement the state mach= ine + * in the PnvCore. For now, this hack makes things work. + */ + if (chiptod->tod_state !=3D tod_running) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_MOVE_TOD_TO_TB_REG in bad state %d\n", + chiptod->tod_state); + } else if (!(val & PPC_BIT(0))) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_MOVE_TOD_TO_TB_REG with bad val 0x%" PRIx6= 4"\n", + val); + } else if (chiptod->slave_pc_target =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_MOVE_TOD_TO_TB_REG with no slave target\n"= ); + } else { + PowerPCCPU *cpu =3D chiptod->slave_pc_target->threads[0]; + CPUPPCState *env =3D &cpu->env; + + /* + * Moving TOD to TB will set the TB of all threads in a + * core, so skiboot only does this once per thread0, so + * that is where we keep the timebase state machine. + * + * It is likely possible for TBST to be driven from other + * threads in the core, but for now we only implement it for + * thread 0. + */ + + if (env->tb_ready_for_tod) { + env->tod_sent_to_tb =3D 1; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write r= eg" + " TOD_MOVE_TOD_TO_TB_REG with TB not ready t= o" + " receive TOD\n"); + } + } + break; case TOD_START_TOD_REG: if (chiptod->tod_state !=3D tod_stopped) { qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in " @@ -347,6 +477,7 @@ static void pnv_chiptod_power9_class_init(ObjectClass *= klass, void *data) xdc->dt_xscom =3D pnv_chiptod_power9_dt_xscom; =20 pctc->broadcast_ttype =3D chiptod_power9_broadcast_ttype; + pctc->tx_ttype_target =3D chiptod_power9_tx_ttype_target; =20 pctc->xscom_size =3D PNV_XSCOM_CHIPTOD_SIZE; pctc->xscom_ops =3D &pnv_chiptod_power9_xscom_ops; @@ -399,6 +530,7 @@ static void pnv_chiptod_power10_class_init(ObjectClass = *klass, void *data) xdc->dt_xscom =3D pnv_chiptod_power10_dt_xscom; =20 pctc->broadcast_ttype =3D chiptod_power10_broadcast_ttype; + pctc->tx_ttype_target =3D chiptod_power10_tx_ttype_target; =20 pctc->xscom_size =3D PNV_XSCOM_CHIPTOD_SIZE; pctc->xscom_ops =3D &pnv_chiptod_power10_xscom_ops; --=20 2.42.0