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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id h21-20020a170902eed500b001bc21222e34sm1680760plb.285.2023.11.23.11.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 11:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700766944; x=1701371744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ulovx9Gb5ru7ZFkz+gHPuuib2emkH4We+Ds4Yk+nbEs=; b=NLceFD8ph1rBGcvOSFFgFYOk1cy+JQdqWEWp7PujR+muc6maxMlnQWF4Gqz0EEIIny B4lmcRG+X18FfrrnhYk5IEdOu1d6oJT/Y3G8r+JBPXZZFTLzDFDoUPagDlFpMbYRwb+y Ztou7qrlz+BxggDQgfqev+sYgPy3M9FyaNzrI9SBshHYen5pD+Q0Lzl3uXpQ99Hfp7Ky UIcz2p2F4+qmnjMHF9vkd9WOfEWWl5mMNaDBqLyENubz41J4XiJoDpPdUkc0w3RgmMa3 ZA4BtP0Xu1OFkGOX+jSwblZH3tLiJpyWgfDFfKlhiZ5fBCAUUAOm+WOkwJixV+RsMHVc JUEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700766944; x=1701371744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulovx9Gb5ru7ZFkz+gHPuuib2emkH4We+Ds4Yk+nbEs=; b=DaT+ox99yp1nOXEuOwoDdtLmPA2OfYTggVrZr4glGJru29SXvNDIAeCqXL1CZB83Do 48Qa7volNJ6/3zsa+cn1gBG3l/7q10AFu0OhUU4xeUcD6hoOAwohMU7c1v+ENI04cFsL xPWJQkJT437hX+GJjayPnR9KUvQX3VJIcVPSdlJS2tNP9n80UV/j8wmTKDnmXV8ORfBh 3mUbzLqYBwgY1XFoX4Kr0qhkT+me83uW0b3Tfaqt324Y4LlwFBR6B+3FYnsHi9GSrOIR ZcwWkEPniRnSHJAjDDAupou89JGTozf/sKf3ZOg8r7E7nq5GDBVgK9qIpLJyXvKuWcVX r04Q== X-Gm-Message-State: AOJu0YxbzJNJHH3/i0nK1FeQqhHWQ6OlzeuovvYkNI43hessyZSogTH/ Ibu0J74xKfe/hcqQBwQ6hHck4glBIrCdyjiO0uA= X-Google-Smtp-Source: AGHT+IHD0oDq70RTenfG1UkGNIV1uTD4hNApISIuR+xRkY9vwUj0JTRjVoYel0L0jiZGetPBQwmtQA== X-Received: by 2002:a17:902:ea84:b0:1cf:65e1:b754 with SMTP id x4-20020a170902ea8400b001cf65e1b754mr423361plb.16.1700766944621; Thu, 23 Nov 2023 11:15:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 2/7] target/riscv: add priv ver restriction to profiles Date: Thu, 23 Nov 2023 16:15:27 -0300 Message-ID: <20231123191532.1101644-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123191532.1101644-1-dbarboza@ventanamicro.com> References: <20231123191532.1101644-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700767038356100003 Content-Type: text/plain; charset="utf-8" Some profiles, like RVA22S64, has a priv_spec requirement. Make this requirement explicit for all profiles. We'll validate this requirement finalize() time and, in case the user chooses an incompatible priv_spec while activating a profile, a warning will be shown. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/tcg/tcg-cpu.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 59b131c1fc..29a9f77702 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1537,6 +1537,7 @@ Property riscv_cpu_options[] =3D { static RISCVCPUProfile RVA22U64 =3D { .name =3D "rva22u64", .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, .ext_offsets =3D { CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5ff629650d..1f34eda1e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,10 +81,12 @@ typedef struct riscv_cpu_profile { uint32_t misa_ext; bool enabled; bool user_set; + int priv_spec; const int32_t ext_offsets[]; } RISCVCPUProfile; =20 #define RISCV_PROFILE_EXT_LIST_END -1 +#define RISCV_PROFILE_ATTR_UNUSED -1 =20 extern RISCVCPUProfile *riscv_profiles[]; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ddf37b25f3..a26cc6f093 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -74,6 +74,20 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint= 32_t bit, } } =20 +static const char *cpu_priv_ver_to_str(int priv_ver) +{ + switch (priv_ver) { + case PRIV_VERSION_1_10_0: + return "v1.10.0"; + case PRIV_VERSION_1_11_0: + return "v1.11.0"; + case PRIV_VERSION_1_12_0: + return "v1.12.0"; + } + + g_assert_not_reached(); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -764,11 +778,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_profile(RISCVCPU *cpu, RISCVCPUProfile *profile) { + CPURISCVState *env =3D &cpu->env; const char *warn_msg =3D "Profile %s mandates disabled extension %s"; bool send_warn =3D profile->user_set && profile->enabled; bool profile_impl =3D true; int i; =20 + if (profile->priv_spec !=3D env->priv_ver) { + profile_impl =3D false; + + if (send_warn) { + warn_report("Profile %s requires priv spec %s, " + "but priv ver %s was set", profile->name, + cpu_priv_ver_to_str(profile->priv_spec), + cpu_priv_ver_to_str(env->priv_ver)); + } + } + for (i =3D 0; misa_bits[i] !=3D 0; i++) { uint32_t bit =3D misa_bits[i]; =20 @@ -1057,6 +1083,10 @@ static void cpu_set_profile(Object *obj, Visitor *v,= const char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + if (profile->enabled) { + cpu->env.priv_ver =3D profile->priv_spec; + } + for (i =3D 0; misa_bits[i] !=3D 0; i++) { uint32_t bit =3D misa_bits[i]; =20 --=20 2.41.0