From nobody Wed Nov 27 06:30:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765664; cv=none; d=zohomail.com; s=zohoarc; b=P/D4W6lr56x0Q5uStuCOJDRxsg4eIxaRiS58XOFvmO2SeWlR2a+eIBq0VyI3zHENS8k1WiIkulQIdfaFsVxJ7YQM/v/HGjZeKDWDwgpuMiM4VE0026SBZC/sm7Kr1bHQNBizYuyGB7hCoKWj263ZOiQAuIxBxqeV/R9vmFITSkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765664; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=ho61mg5TxV99QdFbj7E+Bw3UMFZafJ6l6JnMsL/oEZ3R8CIShuh6M/mc2hvrS7uY0qWUZgONQk0WSZqL1mTYjamrxd/lPd9Gp+LhmkpKwnjTRRdUFGmOr91AXmVDQTQVCi2SOsTNLpduVCpX0jypFJ/evCe2wQiN7qJu36jSGyc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170076566424471.50588499454796; Thu, 23 Nov 2023 10:54:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoH-0000KG-U3; Thu, 23 Nov 2023 13:52:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoF-00005h-Ev for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:19 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6EoD-0000Dt-JO for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:19 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1cf50cc2f85so9143905ad.1 for ; Thu, 23 Nov 2023 10:52:17 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765535; x=1701370335; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=aTitXhPj5uE6X6ftuc71czfhdFQvRSGL+5UQ6fjNzEFFKZmWgHOSNTJncp7iPAeo2v j1dLZe5sRIitRzR5pYPeCYz7QUiy9IlwcvqQXxvHrrJfSF/ng7CNFT/x685vUhbjiEB3 BsZoUf/FqR9T7l0mpbq6Jt3SzFNoxts+i1cURQQXBkIwSMfiAkBXYzH2uY3VRyAKlwvp TfSPAHNMQc851zqpKQ8m8CkWqp1kQLyCKpUgyWMpTUGrtmPkua9zSvkLAKna/ng0SZSP UQJ7au7UsTuprHmxOpyr2XLpBYjGDoBgPGH28XgOLUAioqt+yLCn9tjNwGWX1RRapsN5 hOHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765535; x=1701370335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=p9aDZtO7Fjq6I5QHwga7Tk7FMix89wgDU7PTdHX/GtLTC+DsgzXWUPdzRNoOvN4+oL PzSti8EoClAn84MxkA43+oX2iXvlxSz/W8wvoCAJwWlMQoDjkLdV5c+Gd5pWLl1cinMr LjQC8SBupNGCITuge2qoQleHH1cUjPvWljUFTA7f+G4OD76CRR44MPIXCMdc75+CwhnW lv2BSJseeq9lRS0Wzp8R/YojrURKeyHx6CURm6ARy3vln4tkW+ARQalwTBUzPOJQoC+l 2BHiGSLxhQcirxyG7UlRq7u3G1Jhrr/LZVAWeVA6N7YsYDrdJQH63lRg+8KJWu9p3IvJ EzUQ== X-Gm-Message-State: AOJu0YyWVsXC+EXRq7+vHgonwEdE8sr09G4gSh7SXIqdLHEVWlj/OJLF W26bkGQoIR2FQZqzHHlMu6sRmvS6BUvaZwTQb8s= X-Google-Smtp-Source: AGHT+IFc+dmeu0PocUDpJsiRvar9vuTzbjWnu+ae292O6cT2KmxuTtZxkZi6sr03e6BLeNOFiX148Q== X-Received: by 2002:a17:902:db02:b0:1cf:7911:4619 with SMTP id m2-20020a170902db0200b001cf79114619mr386310plx.49.1700765535294; Thu, 23 Nov 2023 10:52:15 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 15/18] target/riscv/tcg: honor user choice for G MISA bits Date: Thu, 23 Nov 2023 15:51:19 -0300 Message-ID: <20231123185122.1100436-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765665959100009 Content-Type: text/plain; charset="utf-8" RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions in the next patch. We'll do the same thing with RVG now to keep consistency between RVG and profile handling. First and foremost, create a new RVG only helper to avoid clogging riscv_cpu_validate_set_extensions(). We do not want to annoy users with RVG warnings like we did in the past (see 9b9741c38f), thus we'll only warn if RVG was user set and the user disabled a RVG extension in the command line. For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then becomes: - if enabled, do nothing; - if disabled and not user set, enable it; - if disabled and user set, throw a warning that it's a RVG mandatory extension. This same logic will be used for profiles in the next patch. Note that this is a behavior change, where we would error out if the user disabled either zicsr or zifencei. As long as users are explicitly disabling things in the command line we'll let them have a go at it, at least in this step. We'll error out later in the validation if needed. Other notable changes from the previous RVG code: - use riscv_cpu_write_misa_bit() instead of manually updating both env->misa_ext and env->misa_ext_mask; - set zicsr and zifencei directly. We're already checking if they were user set and priv version will never fail for these extensions, making cpu_cfg_ext_auto_update() redundant. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c248944f24..b3bba7887e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) +{ + return g_hash_table_contains(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit)); +} + static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) { g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), @@ -362,6 +368,46 @@ static void riscv_cpu_validate_named_features(RISCVCPU= *cpu) riscv_cpu_validate_zic64b(cpu); } =20 +static void riscv_cpu_validate_g(RISCVCPU *cpu) +{ + const char *warn_msg =3D "RVG mandates disabled extension %s"; + uint32_t g_misa_bits[] =3D {RVI, RVM, RVA, RVF, RVD}; + bool send_warn =3D cpu_misa_ext_is_user_set(RVG); + + for (int i =3D 0; i < ARRAY_SIZE(g_misa_bits); i++) { + uint32_t bit =3D g_misa_bits[i]; + + if (riscv_has_ext(&cpu->env, bit)) { + continue; + } + + if (!cpu_misa_ext_is_user_set(bit)) { + riscv_cpu_write_misa_bit(cpu, bit, true); + continue; + } + + if (send_warn) { + warn_report(warn_msg, riscv_get_misa_ext_name(bit)); + } + } + + if (!cpu->cfg.ext_zicsr) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { + cpu->cfg.ext_zicsr =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zicsr"); + } + } + + if (!cpu->cfg.ext_zifencei) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { + cpu->cfg.ext_zifencei =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zifencei"); + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -371,31 +417,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) && - !cpu->cfg.ext_zicsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) && - !cpu->cfg.ext_zifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true); - - env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; + if (riscv_has_ext(env, RVG)) { + riscv_cpu_validate_g(cpu); } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { --=20 2.41.0