From nobody Wed Nov 27 07:46:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765661; cv=none; d=zohomail.com; s=zohoarc; b=NrGjOwHRnID5CFRHpq8FWBf/LKR6eVmi9fIof9wDOVgAdf5PxGc07Ah4E7A8x8FDeDV/aYyHFE1AUdiIr0XmsmRKQ77kmuCNYPc1Zm/uQxzNFKw1qteU2f8unS2cnl/8iBECZZ8Y+MoF5CBl7TvbrMCnFhFJXb97VB59RmSCihg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765661; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=fBwRW5oP5ebI7biWcyVCNYDdnBijojtQ/bZ1FNVgyuUtctY4hKIJo+gymBKI5DoJ2BVjLubc44Y1gtV6y+B0c1TDz0pHYTZ8SCHtD5BvNwmqXuvkWcWrmQumkeOkRksadE2spQpkdqevQtU1yOXvqmN932GjuM9gNqefP1cNwAw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765661530919.10285211897; Thu, 23 Nov 2023 10:54:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoD-0008Qi-Rj; Thu, 23 Nov 2023 13:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Eo2-00087h-0D for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:07 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enx-00006U-TQ for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:05 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ce5e65ba37so8421935ad.1 for ; Thu, 23 Nov 2023 10:52:00 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765520; x=1701370320; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=JrO45cgrmHZxOJPg57WCuKmK4QtKKU+15tJjhMxP6dn+MrlZ5pJbeiLd8xe9Esn7vU cnmIr7MeLgU/EsQgWjKYYHa7KXde4mkzL9jfrRJLdwxAlVm3ePbgSFT0XIEHRoxtbsSQ 6lxlU3Dg2tUyXb4PhEcxN92Cq4ZUsicRAY8yGlUJGc9Nsf2S8azhzcV5MzyYre/ZTEPX jxhF/rEDqFLbkCvWH+M/GkqEMFVY+CYFYmu9Eaw0whLCZN5RUVuCQUypjuHngk1UhWbK P5v1nG7ZGDN7Psd2eypXwl0VF1eiGc1JOu37G/Ijx07uJDeI5bYPwshTCsDIPHdiYdLC QJyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765520; x=1701370320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=m+NieCbA4SE2np69SpCxr31dCB+VQhW4zkn2qtZbCwbO4uM8lMNM5+OUtxWzu/p643 wBQlX4QGZWDYQbEOEDTYch2TJZJzTEcMH9Z7jOYBrgW7cnDX1KUoTQ1PFQy/oY71su7y W2grS1zBmwNiMKKevy2Wx6bZKJupsuLlj79/WCOaDJ3T4ZSt7xndDuJ12uC3Aa6cUw8y /P3U7ErLSltABQbJwfALtmm2CZYodM1HeJKp99soaiFidU9/rUGkDEv82KWybczqpFqT 1k7pNLkIH0GxMlk0nMQH8t3Vs0LrvLMOf1XbnVjv2Z9Iy3pzPLbmwsKCGK9Ko2HXRLT7 Oq+A== X-Gm-Message-State: AOJu0Yz/0w3eIRREFbOHHcKAmJhkGiWMqBF9uLLw2Yj/3qm/13+8EOzX bEjFyDk2vy7VdG633Lz/Kv+VNSQBRLadjwW+zt8= X-Google-Smtp-Source: AGHT+IHRdxkhpG9nrgsyTjDt1f4MhIafMOoobIp/zcziBd2FBR7l/eCYehkd+c0MicSVh2pzizEmfQ== X-Received: by 2002:a17:902:e542:b0:1ce:5f0d:e573 with SMTP id n2-20020a170902e54200b001ce5f0de573mr173316plf.0.1700765519667; Thu, 23 Nov 2023 10:51:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 10/18] target/riscv/tcg: add user flag for profile support Date: Thu, 23 Nov 2023 15:51:14 -0300 Message-ID: <20231123185122.1100436-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765661998100005 Content-Type: text/plain; charset="utf-8" The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them; - profile support, albeit available for all non-vendor CPUs, will be based on top of the new 'rv64i' CPU. Setting a profile to 'true' means enable all mandatory extensions of this profile, setting it to 'false' will disable all mandatory profile extensions of the CPU, which will obliterate preset defaults. This is not a problem for a bare CPU like rv64i but it can allow for silly scenarios when using other CPUs. E.g. an user can do "-cpu rv64,rva22u64=3Dfalse" and have a bunch of default rv64 extensions disabled. The recommended way of using profiles is the rv64i CPU, but users are free to experiment. For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. At this point we can boot a Linux buildroot using rva22u64 using the following options: -cpu rv64i,rva22u64=3Dtrue,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue Note that being an usermode/application profile we still need to explicitly set 's=3Dtrue' to enable Supervisor mode to boot Linux. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 68577da8a8..f26dc7748d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -127,6 +127,19 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_= offset) return false; } =20 +static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) +{ + switch (feat_offset) { + case CPU_CFG_OFFSET(zic64b): + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + break; + default: + g_assert_not_reached(); + } +} + static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -890,6 +903,71 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) } } =20 +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (riscv_cpu_is_vendor(obj)) { + error_setg(errp, "Profile %s is not available for vendor CPUs", + profile->name); + return; + } + + if (cpu->env.misa_mxl !=3D MXL_RV64) { + error_setg(errp, "Profile %s only available for 64 bit CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + profile->user_set =3D true; + profile->enabled =3D value; + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + ext_offset =3D profile->ext_offsets[i]; + + if (profile->enabled) { + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + riscv_cpu_enable_named_feat(cpu, ext_offset); + } + + cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + bool value =3D profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + const RISCVCPUProfile *profile =3D riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -1017,6 +1095,8 @@ static void riscv_cpu_add_user_properties(Object *obj) =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); =20 + riscv_cpu_add_profiles(obj); + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { qdev_property_add_static(DEVICE(obj), prop); } --=20 2.41.0