From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700750476; cv=none; d=zohomail.com; s=zohoarc; b=aY7Ayg10d4sdz8vycLXaJiLLMTMqyWkkgjgTMzaXCrUPhcrypSKf8SrN1feZiDhQPVCbo+LRB/mXf0MlGtAHFCJ6bVPgbaMopwYoCvfGyFG8gcR3X6eSRKPR+i0ckhG6pKB1AMiSEf1eis23d22A1ZDiEIDT2/kb706rXy1ROlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700750476; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; b=PZKd0hAIep+i4fMhhh7S4zpW9sLN7xAV0E3rA9TtO+JjAhrl9UwW8cljlLGCzP1QXFMZccBUtxfrVMnH1PF/xwXxt7NEQ/prKFz4+D9CCr3qPtYNUmaSGaRInOE7btML+9RgcuapFk/u3f34tpM9dhqGD0D/5B5KBlBTdyZGQVk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700750476087100.57329291374936; Thu, 23 Nov 2023 06:41:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Aqy-00020Z-Lt; Thu, 23 Nov 2023 09:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Aqi-0001oO-8t for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:41 -0500 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqa-0002QM-P6 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:31 -0500 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-507be298d2aso1193933e87.1 for ; Thu, 23 Nov 2023 06:38:28 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id a7-20020a056000100700b00332d32efff5sm1791257wrx.74.2023.11.23.06.38.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750306; x=1701355106; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; b=aBUIrDKLC3IQK0EYP/p1YT1iG3z/EEKUTBBt8iiZOH8ERfkIFUf3MdNf5EziD5GwOz gEH61vlNqPSg2Ksvp8OOQPRbeByn7YGPbcBkt2Zr6xmhpLd8vaP04fNtPw6IVShh4fmR bnOhm2Ls4SEDdszKOGnELGzAIc/cQc2BNkUbiLXX+4gIg1ROa1ppErWsh2PtKGhIZcQb ngQc9RluMGVOSbSBXkUyUM+ONNOV3m8ENdAwUVEr5MZs8GoPOQTTM697QQdX82KtcbYR 8HfVyXtmFhei84Pl5/a93N24v7JRKn7t5p5AhSLvYiU+7BX/0VVHkWvnIKM4Y0nykFcQ IwCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750306; x=1701355106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vpz6WqSYEj1xbsU7bl0EFtxY0Jdo72CGKjloYLxmr9U=; b=AOqd56C0lyk7AxXoTnvwGP7g6FiAeG8Eea4S8QAOOmBbEZU8EIbaADaMuIx1yXsp9L 0ny7VV1iuLu0JAvcsKh3atquMrB3Lq85VszDcAaP4x5iB3svq9/0N7/SWarVFRXNkk1c 7faTE+kxgjCIb+hHykFKoroSnaZiivqEmgSOfymWem20G22Fp9HOvbAE0cHzKF0GFatc 19LzKFy0FpU2zYeQxe7cJAcm/VAi1VZ4DJvHBGlsSm/jPk34n6tSug4pbs6PhkTKZy/b ny0m2N8sS6tJdI71ldwnN+MKFiHsOklKisvHJcDmcjBwYamb4mhKq1GqzUs5Ph+9Y+Rz qAYQ== X-Gm-Message-State: AOJu0YymVXZEA3R2bGReeRq/5UwCcc9p/GjFtLlXgKb4j3Plz1i59nAp g/IPsnkJ/njN37gKDH1q/XBiYQ== X-Google-Smtp-Source: AGHT+IGz8ls8p48wUH7A0TIP10jvxIAnuZkwb3v8olBLihV4O0vpBX6eDqhfDzSm29WOvrYyT8WFJg== X-Received: by 2002:ac2:4348:0:b0:509:4c7b:c734 with SMTP id o8-20020ac24348000000b005094c7bc734mr3655236lfl.20.1700750306459; Thu, 23 Nov 2023 06:38:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 1/8] hw/ppc/spapr_cpu_core: Access QDev properties with proper API Date: Thu, 23 Nov 2023 15:38:05 +0100 Message-ID: <20231123143813.42632-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750476582100005 CPUState::start_powered_off field is part of the internal implementation of a QDev CPU. It is exposed as the QDev "start-powered-off" property. External components should use the qdev properties API to access it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Harsh Prateek Bora --- hw/ppc/spapr_cpu_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 91fae56573..24f759ba26 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -306,7 +306,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, = int i, Error **errp) * All CPUs start halted. CPU0 is unhalted from the machine level rese= t code * and the rest are explicitly started up by the guest using an RTAS c= all. */ - cs->start_powered_off =3D true; + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); cs->cpu_index =3D cc->core_id + i; if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { return NULL; --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700750446; cv=none; d=zohomail.com; s=zohoarc; b=cEwuOKg/HTwwBsNM0CPgbvQ7RSePBB/6wuAvix9blRWZ+qhGHVrJkFBZnvA1rUkLRlslCO4GITFVlhnBVjtL3qsAhBrd6wbiWQ0JHznGiqZVOGWzJ4BP09yZ05EmWEYFqukSJm/KS3qIeNMzSd9xWcuDM7cilAZaKA7vEkOdbes= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700750446; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; b=W0sMa+TBdQ2WxAITJnNrg1W0JG3kfpx//FUOpiNcw1fX2IFgLpzfUhYc3e2q0py5XrkzWRGatvhwET4ZrUB3Nu1qHiOl8+1vedYuSeq7iYngePn+phlf4saX/UaoqrjVsa9gIO+9rf6ReVllRFSHi67yikwyNc+YPlc3NcQvdV0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170075044675326.551124455478885; Thu, 23 Nov 2023 06:40:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Aqy-00020T-LY; Thu, 23 Nov 2023 09:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Aqm-0001od-Fq for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:41 -0500 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Aqi-0002RU-Sw for qemu-devel@nongnu.org; Thu, 23 Nov 2023 09:38:40 -0500 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50aaaf6e58fso1326275e87.2 for ; Thu, 23 Nov 2023 06:38:35 -0800 (PST) Received: from m1x-phil.lan ([176.176.165.237]) by smtp.gmail.com with ESMTPSA id k24-20020a5d5258000000b00332c0aace23sm1817937wrc.105.2023.11.23.06.38.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 23 Nov 2023 06:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700750314; x=1701355114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; b=hsUBkAF15u2tF6OaS0hC6R0TUs+duo0yNyVuE+uBDj02b3LY9nm2WDm7BjuNN7uxZ0 xGg8Ja7cPXljTX6Axmxqwmb1BIFHVnvTI7BugnD/5SIiO72UZvXpuAR6flM7Za8X8YE0 G0au7mLeFJKbiKhMgAQgOk/yZdaq8NJOrFIFXEi+5IunjSffwPY7Un7hyyNy6FPtdzMb xnxTGzmJXaFyHXjsbyF7DwF/uTwWFU4Dt+2bDaryx84TlJxWfCBXOR/KT7drc9ty8xPS VURozB1UzQ1RoS5lsvZE72UjaMlMldoQCDDvhrvzz27a9poDcFseJqsr4UPbCTmSLk7J 0ZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750314; x=1701355114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77fFdvJTmm2pNTXteaORtoV0izbQYF6N9SGikVs/zTs=; b=hF2e4o47EISeqak5YqwfMWIZlaBz+8faPJQGnx5w7q04431VRfXuzqII2g+gmWW4xy RRitD6pIZvq9WS2EIkuvwNU4o3yYdtqzaZp/rpyUgM3+h5cvV4vgNiVkbzwyJV8B1Xek G9ZlwBqwx6raQkib86dZy3vACL2ZvwLX+LyRTSwUn7lyABH8IKP8QxXSsHkVgC22Zny4 QntAZUVASxo1wyL6YgqXMmVisH6DjCSYeL/DSQsRr3hhKekLSx2Ffq82XNfJDDYg+tHV MEX7Ist9sluDAKvb2lTJmQ358/WGmtR4FPp3mC1N1zpM0pBdV/oKR5309gHNEZeUzuK/ KhEA== X-Gm-Message-State: AOJu0YwIe85zu8Kco23HGKbuaqZv2xRwVupr8u+uk5gW41ZDlhmw1KtR 7h5w56htDj0C0S3Ym1/JZCgkOw== X-Google-Smtp-Source: AGHT+IHbXqTFASZF9Pt3So9OvTYn+FgWv3Pi+XqIsfiHaLOmxK/IaoO8oRPSYUlieK9SzED+rzMRuQ== X-Received: by 2002:a05:6512:4894:b0:50a:a9ec:1897 with SMTP id eq20-20020a056512489400b0050aa9ec1897mr2523896lfb.35.1700750314699; Thu, 23 Nov 2023 06:38:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 2/8] hw/arm/bcm2836: Simplify use of 'reset-cbar' property Date: Thu, 23 Nov 2023 15:38:06 +0100 Message-ID: <20231123143813.42632-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=philmd@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750448626100003 bcm2836_realize() is called by - bcm2836_class_init() which sets: bc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7") - bcm2837_class_init() which sets: bc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53") Both Cortex-A7 / A53 have the ARM_FEATURE_CBAR set. If it isn't, then this is a programming error: use &error_abort. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 166dc896c0..a1bd1406e1 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -131,10 +131,8 @@ static void bcm2836_realize(DeviceState *dev, Error **= errp) s->cpu[n].core.mp_affinity =3D (bc->clusterid << 8) | n; =20 /* set periphbase/CBAR value for CPU-local registers */ - if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", - bc->peri_base, errp)) { - return; - } + object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", + bc->peri_base, &error_abort); =20 /* start powered off if not enabled */ if (!object_property_set_bool(OBJECT(&s->cpu[n].core), --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 3/8] hw/arm/bcm2836: Use ARM_CPU 'mp-affinity' property Date: Thu, 23 Nov 2023 15:38:07 +0100 Message-ID: <20231123143813.42632-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750420505100003 The 'mp-affinity' property is present since commit 15a21fe028 ("target-arm: Add mp-affinity property for ARM CPU class"). Use it and remove a /* TODO */ comment. Since all ARM CPUs have this property, use &error_abort, because this call can not fail. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index a1bd1406e1..289c30e6b6 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -127,8 +127,8 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); =20 for (n =3D 0; n < BCM283X_NCPUS; n++) { - /* TODO: this should be converted to a property of ARM_CPU */ - s->cpu[n].core.mp_affinity =3D (bc->clusterid << 8) | n; + object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", + (bc->clusterid << 8) | n, &error_abort); =20 /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 4/8] hw: Simplify accesses to the CPUState::'start-powered-off' property Date: Thu, 23 Nov 2023 15:38:08 +0100 Message-ID: <20231123143813.42632-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750402604100001 The 'start-powered-off' property has been added to ARM CPUs in commit 5de164304a ("arm: Allow secondary KVM CPUs to be booted via PSCI"), then eventually got generalized to all CPUs in commit c1b701587e ("target/arm: Move start-powered-off property to generic CPUState"). Since all CPUs have it, no need to check whether it is available. Updating this property can't fail, so use &error_abort. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/armsse.c | 6 ++---- hw/arm/armv7m.c | 8 ++------ hw/arm/bcm2836.c | 8 ++------ hw/mips/cps.c | 7 +++---- hw/ppc/e500.c | 2 +- hw/sparc/sun4m.c | 2 +- 6 files changed, 11 insertions(+), 22 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 31acbf7347..4672df180f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -1022,10 +1022,8 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) * later if necessary. */ if (extract32(info->cpuwait_rst, i, 1)) { - if (!object_property_set_bool(cpuobj, "start-powered-off", tru= e, - errp)) { - return; - } + object_property_set_bool(cpuobj, "start-powered-off", true, + &error_abort); } if (!s->cpu_fpu[i]) { if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index d10abb36a8..cbaebe9bf8 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -318,12 +318,6 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) return; } } - if (object_property_find(OBJECT(s->cpu), "start-powered-off")) { - if (!object_property_set_bool(OBJECT(s->cpu), "start-powered-off", - s->start_powered_off, errp)) { - return; - } - } if (object_property_find(OBJECT(s->cpu), "vfp")) { if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)= ) { return; @@ -334,6 +328,8 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) return; } } + object_property_set_bool(OBJECT(s->cpu), "start-powered-off", + s->start_powered_off, &error_abort); =20 /* * Real M-profile hardware can be configured with a different number of diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 289c30e6b6..b0674a22a6 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -135,12 +135,8 @@ static void bcm2836_realize(DeviceState *dev, Error **= errp) bc->peri_base, &error_abort); =20 /* start powered off if not enabled */ - if (!object_property_set_bool(OBJECT(&s->cpu[n].core), - "start-powered-off", - n >=3D s->enabled_cpus, - errp)) { - return; - } + object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-o= ff", + n >=3D s->enabled_cpus, &error_abort); =20 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { return; diff --git a/hw/mips/cps.c b/hw/mips/cps.c index b6612c1762..4f12e23ab5 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -78,10 +78,9 @@ static void mips_cps_realize(DeviceState *dev, Error **e= rrp) CPUMIPSState *env =3D &cpu->env; =20 /* All VPs are halted on reset. Leave powering up to CPC. */ - if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", tr= ue, - errp)) { - return; - } + object_property_set_bool(OBJECT(cpu), "start-powered-off", true, + &error_abort); + /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); =20 diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 384226296b..566f1200dd 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -955,7 +955,7 @@ void ppce500_init(MachineState *machine) * when implementing non-kernel boot. */ object_property_set_bool(OBJECT(cs), "start-powered-off", i !=3D 0, - &error_fatal); + &error_abort); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); =20 if (!firstenv) { diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 17bf5f2879..64895aebe3 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -804,7 +804,7 @@ static void cpu_devinit(const char *cpu_type, unsigned = int id, =20 qemu_register_reset(sun4m_cpu_reset, cpu); object_property_set_bool(OBJECT(cpu), "start-powered-off", id !=3D 0, - &error_fatal); + &error_abort); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); cpu_sparc_set_id(env, id); *cpu_irqs =3D qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700750393; cv=none; d=zohomail.com; s=zohoarc; b=lhvwKrSxvM8KAe6nTsFAUJc3LQdVfoyMQINCWNUsJ0vSxQkGpfLBWcpD/2WiO4E79hR+VaiAB9zh38SG+1+NZQNhHWpZO7cuf9GbohVCuTlnOnizd5LVGHZoeNJ1QcrZE2ysiYTpEM71gqv09mZ02ULFIXamAyFUxwnjJPCD1ZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700750393; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700750339; x=1701355139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W/6GhqTQcfqlcNRrFtgYEKVU2TeYfnuYg2H0Cp/aYxk=; b=AyArZLCzp6GCsDcfyOcWsIwDnSjy97P/1+ydi3NR3gcpMV+DwgRnQ9fliK9ho+hiS3 MZVX31WpuVqRQ82OUT5vJEAwvWmJj8coyamIksTRBNwuIQQSu+mExVnvFQGkSpof90U5 UkAnEIJgJ9MWTaBCgGECH/vTXwyfiGwofJ4cqBF1rP/ycjuCzQm/e/ds9i6/vnzQKmCh ARWhGPgma80q4NfTBdrR+S39ZduBpv+wO/gAonp8qNyh/eT5jc4/WbvXuktyQxM63cIc W8vp2r/F+eECqzOMRrHlKa6FuYH/IjKCBKUf42P8kvulaC04rJ/bkQNDoJwvfZjaUFFf YhKw== X-Gm-Message-State: AOJu0YzJibAo9E987dFAB49rV8IkH5Panh2Uq8XePb1WsPgHKkmBW7Kl vGj1oeM2gqZbK3aLOI4Bwym7Kw== X-Google-Smtp-Source: AGHT+IF1dfvgy6zCwcWwYaRCEbreWTwH0JKzhVVibbIlbk6FaYCSdBSWG06/JRd88cl7iJjon/AYyA== X-Received: by 2002:adf:e852:0:b0:332:e6ec:8306 with SMTP id d18-20020adfe852000000b00332e6ec8306mr427376wrn.25.1700750338912; Thu, 23 Nov 2023 06:38:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 5/8] hw: Prefer qdev_prop_set_bit over object_property_set_bool for QDev Date: Thu, 23 Nov 2023 15:38:09 +0100 Message-ID: <20231123143813.42632-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750394691100001 The QOM API is lower level than the QDev one. When an instance is QDev and setting the property can not fail (using &error_abort), prefer qdev_prop_set_bit() over object_property_set_bool(). Mechanical transformation using the following coccinelle patch: @@ expression o, p, v; @@ - object_property_set_bool(OBJECT(o), p, v, &error_abort) + qdev_prop_set_bit(DEVICE(o), p, v) @@@@ - object_property_set_bool(o, p, v, &error_abort) + qdev_prop_set_bit(DEVICE(o), p, v) manually adding the missing "hw/qdev-properties.h" header. In hw/arm/armsse.c we use the available 'cpudev' instead of 'cpuobj'. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ani Sinha Reviewed-by: Harsh Prateek Bora Reviewed-by: Peter Maydell --- hw/acpi/cpu_hotplug.c | 7 +++---- hw/acpi/ich9.c | 4 ++-- hw/acpi/piix4.c | 4 ++-- hw/arm/armsse.c | 3 +-- hw/arm/armv7m.c | 3 +-- hw/arm/aspeed_ast2400.c | 3 +-- hw/arm/aspeed_ast2600.c | 9 +++------ hw/arm/bcm2835_peripherals.c | 3 +-- hw/arm/bcm2836.c | 4 ++-- hw/arm/boot.c | 4 ++-- hw/arm/fsl-imx25.c | 3 +-- hw/arm/fsl-imx31.c | 3 +-- hw/arm/fsl-imx6.c | 12 ++++-------- hw/arm/fsl-imx6ul.c | 8 ++++---- hw/arm/fsl-imx7.c | 10 ++++------ hw/arm/npcm7xx.c | 9 +++------ hw/arm/xlnx-versal.c | 9 +++------ hw/arm/xlnx-zynqmp.c | 9 +++------ hw/core/bus.c | 2 +- hw/core/qdev.c | 2 +- hw/i386/pc_piix.c | 19 ++++++------------- hw/microblaze/petalogix_ml605_mmu.c | 5 ++--- hw/microblaze/xlnx-zynqmp-pmu.c | 18 +++++++----------- hw/mips/cps.c | 3 +-- hw/ppc/e500.c | 3 +-- hw/ppc/spapr_pci.c | 3 +-- hw/rx/rx-gdbsim.c | 4 ++-- hw/sparc/sun4m.c | 3 +-- 28 files changed, 64 insertions(+), 105 deletions(-) diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c index 634bbecb31..1338c037b5 100644 --- a/hw/acpi/cpu_hotplug.c +++ b/hw/acpi/cpu_hotplug.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "hw/acpi/cpu_hotplug.h" #include "qapi/error.h" +#include "hw/qdev-properties.h" #include "hw/core/cpu.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" @@ -41,8 +42,7 @@ static void cpu_status_write(void *opaque, hwaddr addr, u= int64_t data, */ if (addr =3D=3D 0 && data =3D=3D 0) { AcpiCpuHotplug *cpus =3D opaque; - object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, - &error_abort); + qdev_prop_set_bit(DEVICE(cpus->device), "cpu-hotplug-legacy", fals= e); } } =20 @@ -66,8 +66,7 @@ static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, C= PUState *cpu) =20 cpu_id =3D k->get_arch_id(cpu); if ((cpu_id / 8) >=3D ACPI_GPE_PROC_LEN) { - object_property_set_bool(g->device, "cpu-hotplug-legacy", false, - &error_abort); + qdev_prop_set_bit(DEVICE(g->device), "cpu-hotplug-legacy", false); return; } =20 diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 25e2c7243e..64b00673fe 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -30,6 +30,7 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/timer.h" +#include "hw/qdev-properties.h" #include "hw/core/cpu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -197,8 +198,7 @@ static bool vmstate_test_use_cpuhp(void *opaque) static int vmstate_cpuhp_pre_load(void *opaque) { ICH9LPCPMRegs *s =3D opaque; - Object *obj =3D OBJECT(s->gpe_cpu.device); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abor= t); + qdev_prop_set_bit(DEVICE(s->gpe_cpu.device), "cpu-hotplug-legacy", fal= se); return 0; } =20 diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index dd523d2e4c..215929ac6a 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -203,8 +203,8 @@ static bool vmstate_test_use_cpuhp(void *opaque) =20 static int vmstate_cpuhp_pre_load(void *opaque) { - Object *obj =3D OBJECT(opaque); - object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abor= t); + DeviceState *dev =3D DEVICE(opaque); + qdev_prop_set_bit(dev, "cpu-hotplug-legacy", false); return 0; } =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 4672df180f..546b15e658 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -1022,8 +1022,7 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * later if necessary. */ if (extract32(info->cpuwait_rst, i, 1)) { - object_property_set_bool(cpuobj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(cpudev, "start-powered-off", true); } if (!s->cpu_fpu[i]) { if (!object_property_set_bool(cpuobj, "vfp", false, errp)) { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index cbaebe9bf8..3a6d72b0f3 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -328,8 +328,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) return; } } - object_property_set_bool(OBJECT(s->cpu), "start-powered-off", - s->start_powered_off, &error_abort); + qdev_prop_set_bit(DEVICE(s->cpu), "start-powered-off", s->start_powere= d_off); =20 /* * Real M-profile hardware can be configured with a different number of diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index a4334c81b8..4a247bfcbb 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -420,8 +420,7 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev= , Error **errp) =20 /* Net */ for (i =3D 0; i < sc->macs_num; i++) { - object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ftgmac100[i]), "aspeed", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b965fbab5e..5ec8ad73cd 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -317,10 +317,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) =20 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, &error_abort); - object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, - &error_abort); - object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, - &error_abort); + qdev_prop_set_bit(DEVICE(&a->cpu[i]), "neon", false); + qdev_prop_set_bit(DEVICE(&a->cpu[i]), "vfp-d32", false); object_property_set_link(OBJECT(&a->cpu[i]), "memory", OBJECT(s->memory), &error_abort); =20 @@ -500,8 +498,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) =20 /* Net */ for (i =3D 0; i < sc->macs_num; i++) { - object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ftgmac100[i]), "aspeed", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { return; } diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 0233038b95..c07ca8817b 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -303,8 +303,7 @@ static void bcm2835_peripherals_realize(DeviceState *de= v, Error **errp) &error_abort); object_property_set_uint(OBJECT(&s->sdhci), "capareg", BCM2835_SDHC_CAPAREG, &error_abort); - object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", tr= ue, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->sdhci), "pending-insert-quirk", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { return; } diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index b0674a22a6..1fdc3be6bb 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -135,8 +135,8 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) bc->peri_base, &error_abort); =20 /* start powered off if not enabled */ - object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-o= ff", - n >=3D s->enabled_cpus, &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[n].core), "start-powered-off", + n >=3D s->enabled_cpus); =20 if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { return; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 84ea6a807a..ebed887e5e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include +#include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" #include "sysemu/kvm.h" @@ -1287,8 +1288,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) * CPU. */ if (cs !=3D first_cpu) { - object_property_set_bool(cpuobj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(cpuobj), "start-powered-off", tru= e); } } } diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 9aabbf7f58..fc6a7c8a8b 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -272,8 +272,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error *= *errp) } =20 /* Watchdog */ - object_property_set_bool(OBJECT(&s->wdt), "pretimeout-support", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index def27bb913..71f50ca802 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -171,8 +171,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error *= *errp) { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } }; =20 - object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", fals= e, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-edge-sel", false); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { return; } diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 7dc42cbfe6..17c399a37e 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -128,8 +128,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) =20 /* All CPU but CPU 0 start in power off mode */ if (i) { - object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-of= f", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", tru= e); } =20 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { @@ -288,10 +287,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error *= *errp) }, }; =20 - object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, - &error_abort); - object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-edge-sel", true); + qdev_prop_set_bit(DEVICE(&s->gpio[i]), "has-upper-pin-irq", true); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { return; } @@ -412,8 +409,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) FSL_IMX6_WDOG2_IRQ, }; =20 - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); =20 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR= [i]); diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index e37b69a5e1..4f4f2a6f41 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -410,8 +410,8 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) * and we have to set all properties before calling sysbus_realize(). */ for (i =3D 0; i < FSL_IMX6UL_NUM_ETHS; i++) { - object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", - s->phy_connected[i], &error_abort); + qdev_prop_set_bit(DEVICE(&s->eth[i]), "phy-connected", + s->phy_connected[i]); /* * If the MDIO bus on this controller is not connected, assume the * other controller provides support for it. @@ -542,8 +542,8 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error = **errp) FSL_IMX6UL_WDOG3_IRQ, }; =20 - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", + true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); =20 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 474cfdc87c..3138ffeb08 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -192,8 +192,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) * Secondary CPUs start in powered-down state (and can be * powered up via the SRC system reset controller) */ - object_property_set_bool(o, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(o), "start-powered-off", true); } =20 qdev_realize(DEVICE(o), NULL, &error_abort); @@ -424,8 +423,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) * and we have to set all properties before calling sysbus_realize(). */ for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { - object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", - s->phy_connected[i], &error_abort); + qdev_prop_set_bit(DEVICE(&s->eth[i]), "phy-connected", + s->phy_connected[i]); /* * If the MDIO bus on this controller is not connected, assume the * other controller provides support for it. @@ -513,8 +512,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **= errp) FSL_IMX7_WDOG4_IRQ, }; =20 - object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", - true, &error_abort); + qdev_prop_set_bit(DEVICE(&s->wdt[i]), "pretimeout-support", true); sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); =20 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR= [i]); diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d047..7022df3cfa 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -478,12 +478,10 @@ static void npcm7xx_realize(DeviceState *dev, Error *= *errp) &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "reset-hivecs", true); =20 /* Disable security extensions. */ - object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "has_el3", false); =20 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { return; @@ -613,8 +611,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) } =20 /* USB Host */ - object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->ehci), "companion-enable", true); sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 9600551c44..e3b730f5f5 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -48,8 +48,7 @@ static void versal_create_apu_cpus(Versal *s) obj =3D OBJECT(&s->fpd.apu.cpu[i]); if (i) { /* Secondary CPUs start in powered-down state */ - object_property_set_bool(obj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); } =20 object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.c= pu), @@ -150,8 +149,7 @@ static void versal_create_rpu_cpus(Versal *s) "rpu-cpu[*]", &s->lpd.rpu.cpu[i], XLNX_VERSAL_RCPU_TYPE); obj =3D OBJECT(&s->lpd.rpu.cpu[i]); - object_property_set_bool(obj, "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); =20 object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abor= t); object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.c= pu), @@ -536,8 +534,7 @@ static void versal_create_ospi(Versal *s, qemu_irq *pic) &s->pmc.iou.ospi.dma_src, TYPE_XLNX_CSU_DMA); =20 - object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", - false, &error_abort); + qdev_prop_set_bit(DEVICE(&s->pmc.iou.ospi.dma_src), "is-dst", false); =20 object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), "dma", OBJECT(mr_dac), &error_abort); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a33015..f3ca3a7527 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -237,14 +237,12 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, = XlnxZynqMPState *s, /* * Secondary CPUs start in powered-down state. */ - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), - "start-powered-off", true, &error_abo= rt); + qdev_prop_set_bit(DEVICE(&s->rpu_cpu[i]), "start-powered-off",= true); } else { s->boot_cpu_ptr =3D &s->rpu_cpu[i]; } =20 - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", t= rue, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->rpu_cpu[i]), "reset-hivecs", true); if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { return; } @@ -518,8 +516,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) /* * Secondary CPUs start in powered-down state. */ - object_property_set_bool(OBJECT(&s->apu_cpu[i]), - "start-powered-off", true, &error_abo= rt); + qdev_prop_set_bit(DEVICE(&s->apu_cpu[i]), "start-powered-off",= true); } else { s->boot_cpu_ptr =3D &s->apu_cpu[i]; } diff --git a/hw/core/bus.c b/hw/core/bus.c index c7831b5293..a24ebe5886 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -176,7 +176,7 @@ bool qbus_realize(BusState *bus, Error **errp) =20 void qbus_unrealize(BusState *bus) { - object_property_set_bool(OBJECT(bus), "realized", false, &error_abort); + qdev_prop_set_bit(DEVICE(bus), "realized", false); } =20 static bool bus_get_realized(Object *obj, Error **errp) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 43d863b0c5..f4aa99ed77 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -303,7 +303,7 @@ bool qdev_realize_and_unref(DeviceState *dev, BusState = *bus, Error **errp) =20 void qdev_unrealize(DeviceState *dev) { - object_property_set_bool(OBJECT(dev), "realized", false, &error_abort); + qdev_prop_set_bit(dev, "realized", false); } =20 static int qdev_assert_realized_properly_cb(Object *obj, void *opaque) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index eace854335..6733652120 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -263,20 +263,13 @@ static void pc_init1(MachineState *machine, size_t i; =20 pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); - object_property_set_bool(OBJECT(pci_dev), "has-usb", - machine_usb(machine), &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-acpi", - x86_machine_is_acpi_enabled(x86ms), - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pic", false, - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pit", false, - &error_abort); - qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); - object_property_set_bool(OBJECT(pci_dev), "smm-enabled", - x86_machine_is_smm_enabled(x86ms), - &error_abort); dev =3D DEVICE(pci_dev); + qdev_prop_set_bit(dev, "has-usb", machine_usb(machine)); + qdev_prop_set_bit(dev, "has-acpi", x86_machine_is_acpi_enabled(x86= ms)); + qdev_prop_set_bit(dev, "has-pic", false); + qdev_prop_set_bit(dev, "has-pit", false); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + qdev_prop_set_bit(dev, "smm-enabled", x86_machine_is_smm_enabled(x= 86ms)); for (i =3D 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index fb7889cf67..626f9b0b56 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -88,9 +88,8 @@ petalogix_ml605_init(MachineState *machine) * root instructions */ object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); - object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, - &error_abort); - object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort= ); + qdev_prop_set_bit(DEVICE(cpu), "dcache-writeback", true); + qdev_prop_set_bit(DEVICE(cpu), "endianness", true); qdev_realize(DEVICE(cpu), NULL, &error_abort); =20 /* Attach emulated BRAM through the LMB. */ diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pm= u.c index 5a2016672a..19cc5efee3 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "hw/qdev-properties.h" #include "hw/boards.h" #include "cpu.h" #include "boot.h" @@ -79,19 +80,14 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState *de= v, Error **errp) =20 object_property_set_uint(OBJECT(&s->cpu), "base-vectors", XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-stack-protection", true); object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort); object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abor= t); - object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true, - &error_abort); - object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abo= rt); - object_property_set_bool(OBJECT(&s->cpu), "endianness", true, - &error_abort); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-barrel", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-msr-instr", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-pcmp-instr", true); + qdev_prop_set_bit(DEVICE(&s->cpu), "use-mmu", false); + qdev_prop_set_bit(DEVICE(&s->cpu), "endianness", true); object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b", &error_abort); object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4f12e23ab5..ee2a8d5563 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -78,8 +78,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) CPUMIPSState *env =3D &cpu->env; =20 /* All VPs are halted on reset. Leave powering up to CPC. */ - object_property_set_bool(OBJECT(cpu), "start-powered-off", true, - &error_abort); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", true); =20 /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 566f1200dd..a63d48c512 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -954,8 +954,7 @@ void ppce500_init(MachineState *machine) * Secondary CPU starts in halted state for now. Needs to change * when implementing non-kernel boot. */ - object_property_set_bool(OBJECT(cs), "start-powered-off", i !=3D 0, - &error_abort); + qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i !=3D 0); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); =20 if (!firstenv) { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 6760823e13..266cf6c9e6 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2490,8 +2490,7 @@ static int spapr_switch_one_vga(DeviceState *dev, voi= d *opaque) || object_dynamic_cast(OBJECT(dev), "secondary-vga") || object_dynamic_cast(OBJECT(dev), "bochs-display") || object_dynamic_cast(OBJECT(dev), "virtio-vga")) { - object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, - &error_abort); + qdev_prop_set_bit(dev, "big-endian-framebuffer", be); } return 0; } diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 47c17026c7..53d3d560c8 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -21,6 +21,7 @@ #include "qemu/error-report.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include "hw/qdev-properties.h" #include "hw/loader.h" #include "hw/rx/rx62n.h" #include "sysemu/qtest.h" @@ -103,8 +104,7 @@ static void rx_gdbsim_init(MachineState *machine) &error_abort); object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", rxc->xtal_freq_hz, &error_abort); - object_property_set_bool(OBJECT(&s->mcu), "load-kernel", - kernel_filename !=3D NULL, &error_abort); + qdev_prop_set_bit(DEVICE(&s->mcu), "load-kernel", kernel_filename !=3D= NULL); =20 if (!kernel_filename) { if (machine->firmware) { diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 64895aebe3..d631d555d8 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -803,8 +803,7 @@ static void cpu_devinit(const char *cpu_type, unsigned = int id, env =3D &cpu->env; =20 qemu_register_reset(sun4m_cpu_reset, cpu); - object_property_set_bool(OBJECT(cpu), "start-powered-off", id !=3D 0, - &error_abort); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", id !=3D 0); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); cpu_sparc_set_id(env, id); *cpu_irqs =3D qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 6/8] hw: Simplify uses of qdev_prop_set_bit(dev, 'start-powered-off') Date: Thu, 23 Nov 2023 15:38:10 +0100 Message-ID: <20231123143813.42632-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750422544100005 Simplify few qdev_prop_set_bit("start-powered-off") and re-indent. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/allwinner-h3.c | 3 +-- hw/arm/allwinner-r40.c | 3 +-- hw/arm/bcm2836.c | 4 ++-- hw/arm/fsl-imx6.c | 4 +--- hw/arm/fsl-imx7.c | 12 +++++------- 5 files changed, 10 insertions(+), 16 deletions(-) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f05afddf7e..593244464a 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -251,8 +251,7 @@ static void allwinner_h3_realize(DeviceState *dev, Erro= r **errp) * Disable secondary CPUs. Guest EL3 firmware will start * them via CPU reset control registers. */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", - i > 0); + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", i > 0); =20 /* All exception levels required */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index a0d367c60d..202a158fb8 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -304,8 +304,7 @@ static void allwinner_r40_realize(DeviceState *dev, Err= or **errp) * Disable secondary CPUs. Guest EL3 firmware will start * them via CPU reset control registers. */ - qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", - i > 0); + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", i > 0); =20 /* All exception levels required */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1fdc3be6bb..03e6eb2fb2 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -99,9 +99,9 @@ static void bcm2835_realize(DeviceState *dev, Error **err= p) =20 /* Connect irq/fiq outputs from the interrupt controller. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_I= RQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_F= IQ)); } =20 static void bcm2836_realize(DeviceState *dev, Error **errp) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 17c399a37e..b7f1738a89 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -127,9 +127,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) } =20 /* All CPU but CPU 0 start in power off mode */ - if (i) { - qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", tru= e); - } + qdev_prop_set_bit(DEVICE(&s->cpu[i]), "start-powered-off", i > 0); =20 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { return; diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 3138ffeb08..451801f7e8 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -187,13 +187,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error = **errp) &error_abort); } =20 - if (i) { - /* - * Secondary CPUs start in powered-down state (and can be - * powered up via the SRC system reset controller) - */ - qdev_prop_set_bit(DEVICE(o), "start-powered-off", true); - } + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ + qdev_prop_set_bit(DEVICE(o), "start-powered-off", i > 0); =20 qdev_realize(DEVICE(o), NULL, &error_abort); } --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 7/8] hw/arm/bcm2836: Move code after error checks Date: Thu, 23 Nov 2023 15:38:11 +0100 Message-ID: <20231123143813.42632-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750438562100001 First run the code that can return errors, then on success run what alters the instance state. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2836.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 03e6eb2fb2..e56935f3e5 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -119,13 +119,6 @@ static void bcm2836_realize(DeviceState *dev, Error **= errp) return; } =20 - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); - for (n =3D 0; n < BCM283X_NCPUS; n++) { object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", (bc->clusterid << 8) | n, &error_abort); @@ -158,6 +151,13 @@ static void bcm2836_realize(DeviceState *dev, Error **= errp) qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)= ); } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq",= 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, + qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq",= 0)); } =20 static void bcm283x_class_init(ObjectClass *oc, void *data) --=20 2.41.0 From nobody Wed Nov 27 04:46:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700750473; cv=none; d=zohomail.com; s=zohoarc; b=A0wgpo/8UL+XC1L9xDrn7sDxIU678vc0QrJefBlUEfSqeq1YgUTGcGyahlvJLP9R4ng/nVAjdRGgO3ttY79fdm2ZEzp7tdLYUASxsdI3+UieYu7hcvKTZRF0LrUX6Vm82lLSaoXmAyECz085bEoJsNPMjW6HGmHrD3hmYIL9ZUE= ARC-Message-Signature: i=1; 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Thu, 23 Nov 2023 06:39:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Alistair Francis , Joel Stanley , Artyom Tarasenko , Mark Cave-Ayland , Ani Sinha , Eduardo Habkost , David Gibson , "Michael S. Tsirkin" , Peter Maydell , Andrew Jeffery , Daniel Henrique Barboza , Yoshinori Sato , "Edgar E. Iglesias" , Niek Linnenbank , Andrey Smirnov , Tyrone Ting , Jean-Christophe Dubois , Strahinja Jankovic , Harsh Prateek Bora , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , qemu-ppc@nongnu.org, Hao Wu , Marcel Apfelbaum , Beniamino Galvani , Richard Henderson , Nicholas Piggin Subject: [PATCH-for-9.0 v2 8/8] hw/arm/bcm2836: Add local variable to remove various DEVICE() casts Date: Thu, 23 Nov 2023 15:38:12 +0100 Message-ID: <20231123143813.42632-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123143813.42632-1-philmd@linaro.org> References: <20231123143813.42632-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700750474583100001 Cast the CPU to DeviceState once. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index e56935f3e5..013cee853d 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -120,6 +120,8 @@ static void bcm2836_realize(DeviceState *dev, Error **e= rrp) } =20 for (n =3D 0; n < BCM283X_NCPUS; n++) { + DeviceState *cpudev =3D DEVICE(&s->cpu[n].core); + object_property_set_int(OBJECT(&s->cpu[n].core), "mp-affinity", (bc->clusterid << 8) | n, &error_abort); =20 @@ -128,27 +130,26 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) bc->peri_base, &error_abort); =20 /* start powered off if not enabled */ - qdev_prop_set_bit(DEVICE(&s->cpu[n].core), "start-powered-off", - n >=3D s->enabled_cpus); + qdev_prop_set_bit(cpudev, "start-powered-off", n >=3D s->enabled_c= pus); =20 - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(cpudev, NULL, errp)) { return; } =20 /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); =20 /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, + qdev_connect_gpio_out(cpudev, GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n= )); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, + qdev_connect_gpio_out(cpudev, GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, + qdev_connect_gpio_out(cpudev, GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)= ); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, + qdev_connect_gpio_out(cpudev, GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)= ); } =20 --=20 2.41.0