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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714542; x=1701319342; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XjKPY5uNF9R+Jnwg0amtOzmeSA/AKoApnoQmZc/PaUQ=; b=UZqjOg3SMbaqlEULftfSQsa7+fg4XVRksC+UsKrT62tGLHxzS6yznRc6dWKZkXdmPM BK0yfFPi+T7maOejHTmuECwwvR/v7uZbId5isTJNvpdqxNFSmQAuqgh/2UdP24w+BKGd 16pw7GtDsaKkjLlYYu6nWbFdQYUw2Xw0OURae6wsRg2qS7kLedKn5LB875OfcfCeQHGD T9Mdfez9wRPUaihhg+Sz8xoPuLnwwS2L3PfBsfKYdYX6COhMpIemjrwzpf3MNv5X2lEb 9gXFDyQUIypcbcshNmwVJA8SxgvcIEoPLn7dbP441l4Jd+WExG4lzzg5je/bbbRIQqJD Nk2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714542; x=1701319342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XjKPY5uNF9R+Jnwg0amtOzmeSA/AKoApnoQmZc/PaUQ=; b=BQipcmxQsR7H0AZT9zbyI+dfb8LnMbwTxyQGy0zGcVwFTYraRBhyqIoolJRPJ9nklm BP6+W582wmgGGNkOcnCHXFy4aJTgwxHtfdzYjAWYpXpKUOMRPrB2A4tNud9P5LDBJDVX dFhhlVPA4YUEnSNmKOC5BPjPjCYF2Sh5KchqPnRwR0QkSdzL33GA6+o8bu2DGeAB767h b7JT4/98ygtvv5dc9B3anSf8WL9sdsIE5oalMe96Oh//+1fh3s5YEnYL8CKvPGCmeYUl EcSiJp08/wKIqRhpHrUuXDbLryyM7RvJ0+uQ1byR9Vk6Z/ziLxTO1n0Z+QPilI7Yn4MN sDIg== X-Gm-Message-State: AOJu0YyltEa0tbOq1E8I5b+urhcOcmI4w6N63164x3NUOu8bzRFFeMkl GL/1TuKyOf+CKbxfXw+0SjYN6b5c7ki3N2dMsz+A9QOu X-Google-Smtp-Source: AGHT+IE0sm64WuzXPJHQ3rg9EIWodmeb+ASWtiDwTXwC78Wks3QbHwuH/uqyFEayJwPSG8L8sQxTmA== X-Received: by 2002:a05:6808:1911:b0:3a7:2390:3583 with SMTP id bf17-20020a056808191100b003a723903583mr6301855oib.38.1700714542378; Wed, 22 Nov 2023 20:42:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/21] accel/kvm: Make kvm_has_guest_debug static Date: Wed, 22 Nov 2023 22:41:59 -0600 Message-Id: <20231123044219.896776-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x234.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714727917100001 Content-Type: text/plain; charset="utf-8" This variable is not used or declared outside kvm-all.c. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- accel/kvm/kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index e39a810a4e..f138e7fefe 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -98,7 +98,7 @@ bool kvm_allowed; bool kvm_readonly_mem_allowed; bool kvm_vm_attributes_allowed; bool kvm_msi_use_devid; -bool kvm_has_guest_debug; +static bool kvm_has_guest_debug; static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size =3D ~0; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714606; cv=none; d=zohomail.com; s=zohoarc; b=fpMrntLoQkurYVVDpoTrWhYtWaYBxVAY+FTug3EeAPY7rbh7f4Qm+3SLSCl+YTiw9U4dsMvDmLrSjQ3y1Wh1odW5yCH2yoJKoZ0sMQW48r/hw90Ioj1LyJcUJaVri5xMYaNF8wz0nIEcKwcyzQs5cNTGXCt4qUducb3L25I7UvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714606; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zCITuvk4f7RVKkgdoPWw8dDcnr4IYcKR0RlzuYraGn4=; b=kG2SqgXwc6R5yCKojufrz4wTGscpLvotNnhj8t0862VlJF8KkuhgZ/jsiT6wcMIgB+TPV7wcJWHXfHt/ZX5eQrg4LNYqoPiE4oGG7VfHHkJMFKYfOcvly1LlpTjXX/GG0clEYG7FvX8Tk9lMqysQVrvpxH1OtX70co8/yjxl8FU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714605995507.33642861692726; Wed, 22 Nov 2023 20:43:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61Xo-0006L3-Pb; Wed, 22 Nov 2023 23:42:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xn-0006Ij-D8 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:27 -0500 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xl-00064t-8O for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:27 -0500 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1f0f94a08a0so340734fac.2 for ; Wed, 22 Nov 2023 20:42:24 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714543; x=1701319343; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zCITuvk4f7RVKkgdoPWw8dDcnr4IYcKR0RlzuYraGn4=; b=IS3APXVaoAlhTUnhHb5VPTqDUrh+PJ5Pscz+3UME/Ba/XLDwxk5G/4L2LCn5wDEwih w1jQjql0QmLjMf8Y8mUBp2ppCtbdFbiYFqwHdYwpgmMe5lXfXSU/970x/b71R0xKcRlf ld/nwEl77Eq+sR1YMCjynAgmRZ0ix0HqS3kFZL+y1q+0pHP6oba7En5r+sPLw3Xjfv1b RkidTOmzwAmIHA/YN3qh8Uuz8ki8wuYc7Iuu4TTGUWUesnMv1ucUNibUtGkx1ZGofML0 +aoxux6qtNGCzAwocCximkH7J+RRZ6WHNtiN4vTA/W+RjEemvRRF7KBW+DQA5KWwTg/Z 9yzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714543; x=1701319343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zCITuvk4f7RVKkgdoPWw8dDcnr4IYcKR0RlzuYraGn4=; b=rpt8QXP8yOcJ1FvDD9wIZ+RVdumOD676Y9GNYAdan4mq0MbqmkCSxNaka+HJvcXhOx uiHZjj4W3Z0Oc77K6IAkFX08j/g7DiE1+QDYJt73ZNwu0PLY7lt0vKPBOj6VZCGjry+I eYGVrIpoIl1+QtqbRsSXG/IyBM23lUbPLM9AiejcUNrAsQLcaD8hED/OGzPVRu/9BJSC yIKP0J9XUIH1YKf3HhhwriLnMBkjYbQlcYnmipXIDtgxGDwq4y2ehMWqbHJjRkaxOydN Cu+KwzmB761sHw7LWWef5cCcup+rA5/1ZKK9ZvsUf5TIUwjn4U7oFcyHJf5WcPA5djwS 53RQ== X-Gm-Message-State: AOJu0YwJxr1RcV2siOiMtsQI2F04qP5j9RcC7atH5rBEsKoeQatJoNFV 0HBiPLA9yVJ197iYiCS9VKAFYAw+2U1yw7xQVZ/aTwF7 X-Google-Smtp-Source: AGHT+IH59O0M14Z7pwf1FMoqW7pV5LeBTQ/iX4agRwD6hUX8gkNDNDpo6bDTAEpDOr07q79gP963mQ== X-Received: by 2002:a05:6870:be8c:b0:1f5:7e47:e297 with SMTP id nx12-20020a056870be8c00b001f57e47e297mr6186991oab.11.1700714543289; Wed, 22 Nov 2023 20:42:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Chao Du Subject: [PATCH 02/21] target/arm: kvm64: remove a redundant KVM_CAP_SET_GUEST_DEBUG probe Date: Wed, 22 Nov 2023 22:42:00 -0600 Message-Id: <20231123044219.896776-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714608083100003 Content-Type: text/plain; charset="utf-8" From: Chao Du The KVM_CAP_SET_GUEST_DEBUG is probed during kvm_init(). gdbserver will fail to start if the CAP is not supported. So no need to make another probe here, like other targets. Signed-off-by: Chao Du Reviewed-by: Richard Henderson Message-Id: <20231025070726.22689-1-duchao@eswincomputing.com> Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm64.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3c175c93a7..b8bb25a1ea 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -32,13 +32,9 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" =20 -static bool have_guest_debug; =20 void kvm_arm_init_debug(KVMState *s) { - have_guest_debug =3D kvm_check_extension(s, - KVM_CAP_SET_GUEST_DEBUG); - max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); hw_watchpoints =3D g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); @@ -1141,33 +1137,23 @@ static const uint32_t brk_insn =3D 0xd4200000; =20 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) { - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 0) || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { return -EINVAL; } + return 0; } =20 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) { static uint32_t brk; =20 - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk !=3D brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk !=3D brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { return -EINVAL; } + return 0; } =20 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714652; cv=none; d=zohomail.com; s=zohoarc; b=i7pXOw5Qe3au7CbK2cfOB0eQP2k8D3My3n+tOeTEK2KvmULmlUWXm3eSnUdlEV9O0L5Rzsy810EjAcR2vKTvnJCpYnhTl0rMbvtFfsGSEFtHe4zYtT0gScGsrjaSmTNkOvUpRhJmINoKMhD3kwYNFvcm5T16GmKmDRQ4mxcgzUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714652; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NH7qrfCWzzImD63ZDY8zW+pyuXHpfd4KHpoGwFQ2aTE=; b=JLi/FFHB06by3Rp5VD6Ai/kMeCZz8IDG2qKeHEqD0N+i+7fe17xte1Jw7JaqfSWfIt66+EmaNDEobgnpb1pEGJI6//wmvvy8yWEZrJQKcEkNqUyDyrLqNvCB3prmHr3W37ZjNpS4qZH2J6BRH/CAWirHkQlQTG93M1N5zN6SjIY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714652630827.8338106498385; Wed, 22 Nov 2023 20:44:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YC-0006Vs-3W; Wed, 22 Nov 2023 23:42:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xp-0006LE-Q4 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:30 -0500 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xn-00065r-Rl for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:29 -0500 Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-3b842c1511fso330781b6e.1 for ; Wed, 22 Nov 2023 20:42:27 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714544; x=1701319344; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NH7qrfCWzzImD63ZDY8zW+pyuXHpfd4KHpoGwFQ2aTE=; b=C0mXLp+N/ir6oZPnPJOaQfni1Zcm5hcyzOGL4m7gq9l9pKRUiPwhE8gOpuHGk+INUX P2MlfbxFRo9nEP6uAt2TV/fHKigm0i4EN4PId3sXV4GtYHoeI3XwlJNU/hQs96vhbaW5 IRE0ApQZcr8uQQ+C6Gnec0X/CS1CS87MexdHDHQTHAel5IFHTZcE5U73Y9se6YFA6/m+ JzhfJi/wQjxVOBx3hDtobhQ2EktSJk7XPkFziaXb6i+iZfx9xPkV9NLPRP/Wa//g550w JGtt/f38da+RAlFAL9OvUh94MPzN63pAot+n0ouSEFCbe0AA/qjgxf0Zx1yS4nFDmFLE /6TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714544; x=1701319344; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714653708100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 8 +++++++- target/arm/kvm64.c | 12 ------------ 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 051a0da41c..fe6d824a52 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,14 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_init_debug() - initialize guest debug capabilities - * @s: KVMState - * - * Should be called only once before using guest debug capabilities. - */ -void kvm_arm_init_debug(KVMState *s); - /** * kvm_arm_vcpu_init: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7903e2ddde..b4836da6b2 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -308,7 +308,13 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } =20 - kvm_arm_init_debug(s); + max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); + hw_watchpoints =3D g_array_sized_new(true, true, + sizeof(HWWatchpoint), max_hw_wps); + + max_hw_bps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); + hw_breakpoints =3D g_array_sized_new(true, true, + sizeof(HWBreakpoint), max_hw_bps); =20 return ret; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b8bb25a1ea..40f459b786 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -33,18 +33,6 @@ #include "hw/acpi/ghes.h" =20 =20 -void kvm_arm_init_debug(KVMState *s) -{ - max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); - hw_watchpoints =3D g_array_sized_new(true, true, - sizeof(HWWatchpoint), max_hw_wps); - - max_hw_bps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); - hw_breakpoints =3D g_array_sized_new(true, true, - sizeof(HWBreakpoint), max_hw_bps); - return; -} - int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) { switch (type) { --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714683; cv=none; d=zohomail.com; s=zohoarc; b=hADaC0oazlbbj9DHLgYyx/kiG6Z/VwVeMcDbCUwWPskUdVrF+l9Li3wqDy9cUav2nuEq+0ap8LM0PXPvysnXjShIxzggqqMfmqBS0uxV8gR8Yarkz+mEqSQny9kl7L1iB657GXiIOG5MgGOfJZ7Tjwd5VWd4Czs/VW5dR5ReNVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714683; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714683872100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 10 -------- target/arm/kvm.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 49 ------------------------------------- 3 files changed, 57 insertions(+), 59 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index fe6d824a52..bb284a47de 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -472,14 +472,4 @@ bool kvm_arm_hw_debug_active(CPUState *cs); struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); =20 -/** - * kvm_arm_verify_ext_dabt_pending: - * @cs: CPUState - * - * Verify the fault status code wrt the Ext DABT injection - * - * Returns: true if the fault status code is as expected, false otherwise - */ -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b4836da6b2..696bc63e86 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -793,6 +793,63 @@ int kvm_get_vcpu_events(ARMCPU *cpu) return 0; } =20 +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +/* + * ESR_EL1 + * ISS encoding + * AARCH64: DFSC, bits [5:0] + * AARCH32: + * TTBCR.EAE =3D=3D 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE =3D=3D 1 + * FS, bits [5:0] + */ +#define ESR_DFSC(aarch64, lpae, v) \ + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ + : (((v) >> 6) | ((v) & 0x1F))) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +/** + * kvm_arm_verify_ext_dabt_pending: + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: true if the fault status code is as expected, false otherwise + */ +static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int aarch64_mode =3D arm_feature(env, ARM_FEATURE_AARCH64); + int lpae =3D 0; + + if (!aarch64_mode) { + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae =3D arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + /* + * The verification here is based on the DFSC bits + * of the ESR_EL1 reg only + */ + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) =3D=3D + ESR_DFSC_EXTABT(aarch64_mode, lpae)); + } + return false; +} + void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 40f459b786..7d937e2539 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1213,52 +1213,3 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_d= ebug_exit_arch *debug_exit) =20 return false; } - -#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) -#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) - -/* - * ESR_EL1 - * ISS encoding - * AARCH64: DFSC, bits [5:0] - * AARCH32: - * TTBCR.EAE =3D=3D 0 - * FS[4] - DFSR[10] - * FS[3:0] - DFSR[3:0] - * TTBCR.EAE =3D=3D 1 - * FS, bits [5:0] - */ -#define ESR_DFSC(aarch64, lpae, v) \ - ((aarch64 || (lpae)) ? ((v) & 0x3F) \ - : (((v) >> 6) | ((v) & 0x1F))) - -#define ESR_DFSC_EXTABT(aarch64, lpae) \ - ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) - -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) -{ - uint64_t dfsr_val; - - if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - int aarch64_mode =3D arm_feature(env, ARM_FEATURE_AARCH64); - int lpae =3D 0; - - if (!aarch64_mode) { - uint64_t ttbcr; - - if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { - lpae =3D arm_feature(env, ARM_FEATURE_LPAE) - && (ttbcr & TTBCR_EAE); - } - } - /* - * The verification here is based on the DFSC bits - * of the ESR_EL1 reg only - */ - return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) =3D=3D - ESR_DFSC_EXTABT(aarch64_mode, lpae)); - } - return false; -} --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714671; cv=none; d=zohomail.com; s=zohoarc; b=JmZt+sir9lbi8CBzK3JyVyC0kGdpFe12ZU0ye0eQEKv0Y0Pe3n2vT/sZL8BvWBd95TvYg0a+dpQUouJ+wnz85CCbibhL24/vCzSnMd4/5s5y82XQsu/tOF3E/jLpZc8mU0p65K8P3RjsUUwoRj83A79lQu5DkCYKhsWvvMMmYt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714671; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j7rKkgtczML1NQeakIsfiyCwMRWbdPg9sIsXXpiAu1I=; b=Dh6vsOyVity6zGO05R/y3f0U0L/9Bz9dBY7+72NybY9//JbyoSsQBQgaIyg1fTJ/TMJcFsePlgEYW6DZEOOc3SJvKlQ2GFuZxwhBdWgSt5Yj/u92Ujep4YosVPfdtZ3cFGm1Ak2d06LFilkBbusKmBSuQNixRVn2YVm3d62tDhc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714671081666.7165135596288; Wed, 22 Nov 2023 20:44:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61Y4-0006Nx-Kp; Wed, 22 Nov 2023 23:42:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xr-0006Ld-2Q for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:31 -0500 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xo-00065p-6c for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:30 -0500 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1f937a7b8aaso326081fac.0 for ; Wed, 22 Nov 2023 20:42:27 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714671882100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 24 ++++++++++++++++++++++++ target/arm/kvm64.c | 17 ----------------- 3 files changed, 24 insertions(+), 27 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index bb284a47de..207b7f21b0 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -462,14 +462,4 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_deb= ug_exit_arch *debug_exit); */ bool kvm_arm_hw_debug_active(CPUState *cs); =20 -/** - * kvm_arm_copy_hw_debug_data: - * @ptr: kvm_guest_debug_arch structure - * - * Copy the architecture specific debug registers into the - * kvm_guest_debug ioctl structure. - */ -struct kvm_guest_debug_arch; -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 696bc63e86..2898e680fc 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,30 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 +/** + * kvm_arm_copy_hw_debug_data: + * @ptr: kvm_guest_debug_arch structure + * + * Copy the architecture specific debug registers into the + * kvm_guest_debug ioctl structure. + */ +static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) +{ + int i; + memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); + + for (i =3D 0; i < max_hw_wps; i++) { + HWWatchpoint *wp =3D get_hw_wp(i); + ptr->dbg_wcr[i] =3D wp->wcr; + ptr->dbg_wvr[i] =3D wp->wvr; + } + for (i =3D 0; i < max_hw_bps; i++) { + HWBreakpoint *bp =3D get_hw_bp(i); + ptr->dbg_bcr[i] =3D bp->bcr; + ptr->dbg_bvr[i] =3D bp->bvr; + } +} + void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) { if (kvm_sw_breakpoints_active(cs)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 7d937e2539..ac3120adaf 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,23 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } =20 -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) -{ - int i; - memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); - - for (i =3D 0; i < max_hw_wps; i++) { - HWWatchpoint *wp =3D get_hw_wp(i); - ptr->dbg_wcr[i] =3D wp->wcr; - ptr->dbg_wvr[i] =3D wp->wvr; - } - for (i =3D 0; i < max_hw_bps; i++) { - HWBreakpoint *bp =3D get_hw_bp(i); - ptr->dbg_bcr[i] =3D bp->bcr; - ptr->dbg_bvr[i] =3D bp->bvr; - } -} - bool kvm_arm_hw_debug_active(CPUState *cs) { return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714645751100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 11 +++++++++++ target/arm/kvm64.c | 5 ----- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 207b7f21b0..ac4856cb46 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -454,12 +454,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *c= s) */ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit); =20 -/** - * kvm_arm_hw_debug_active: - * @cs: CPU State - * - * Return: TRUE if any hardware breakpoints in use. - */ -bool kvm_arm_hw_debug_active(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2898e680fc..4608bea7df 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,17 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 +/** + * kvm_arm_hw_debug_active: + * @cs: CPU State + * + * Return: TRUE if any hardware breakpoints in use. + */ +static bool kvm_arm_hw_debug_active(CPUState *cs) +{ + return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); +} + /** * kvm_arm_copy_hw_debug_data: * @ptr: kvm_guest_debug_arch structure diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ac3120adaf..352643e066 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,11 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } =20 -bool kvm_arm_hw_debug_active(CPUState *cs) -{ - return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); -} - static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, const char *name) { --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714645688100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 9 ------ target/arm/kvm.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 70 ---------------------------------------- 3 files changed, 77 insertions(+), 79 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ac4856cb46..9fa9cb7f76 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -445,13 +445,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *c= s) =20 #endif =20 -/** - * kvm_arm_handle_debug: - * @cs: CPUState - * @debug_exit: debug part of the KVM exit structure - * - * Returns: TRUE if the debug exception was handled. - */ -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4608bea7df..55e1b4f26e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -988,6 +988,83 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint= 64_t esr_iss, return -1; } =20 +/** + * kvm_arm_handle_debug: + * @cs: CPUState + * @debug_exit: debug part of the KVM exit structure + * + * Returns: TRUE if the debug exception was handled. + * + * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register + * + * To minimise translating between kernel and user-space the kernel + * ABI just provides user-space with the full exception syndrome + * register value to be decoded in QEMU. + */ +static bool kvm_arm_handle_debug(CPUState *cs, + struct kvm_debug_exit_arch *debug_exit) +{ + int hsr_ec =3D syn_get_ec(debug_exit->hsr); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* Ensure PC is synchronised */ + kvm_cpu_synchronize_state(cs); + + switch (hsr_ec) { + case EC_SOFTWARESTEP: + if (cs->singlestep_enabled) { + return true; + } else { + /* + * The kernel should have suppressed the guest's ability to + * single step at this point so something has gone wrong. + */ + error_report("%s: guest single-step while debugging unsupporte= d" + " (%"PRIx64", %"PRIx32")", + __func__, env->pc, debug_exit->hsr); + return false; + } + break; + case EC_AA64_BKPT: + if (kvm_find_sw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_BREAKPOINT: + if (find_hw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_WATCHPOINT: + { + CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); + if (wp) { + cs->watchpoint_hit =3D wp; + return true; + } + break; + } + default: + error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", + __func__, debug_exit->hsr, env->pc); + } + + /* If we are not handling the debug exception it must belong to + * the guest. Let's re-use the existing TCG interrupt code to set + * everything up properly. + */ + cs->exception_index =3D EXCP_BKPT; + env->exception.syndrome =3D debug_exit->hsr; + env->exception.vaddress =3D debug_exit->far; + env->exception.target_el =3D 1; + qemu_mutex_lock_iothread(); + arm_cpu_do_interrupt(cs); + qemu_mutex_unlock_iothread(); + + return false; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret =3D 0; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 352643e066..6b6db9374c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1121,73 +1121,3 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, stru= ct kvm_sw_breakpoint *bp) } return 0; } - -/* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register - * - * To minimise translating between kernel and user-space the kernel - * ABI just provides user-space with the full exception syndrome - * register value to be decoded in QEMU. - */ - -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit) -{ - int hsr_ec =3D syn_get_ec(debug_exit->hsr); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* Ensure PC is synchronised */ - kvm_cpu_synchronize_state(cs); - - switch (hsr_ec) { - case EC_SOFTWARESTEP: - if (cs->singlestep_enabled) { - return true; - } else { - /* - * The kernel should have suppressed the guest's ability to - * single step at this point so something has gone wrong. - */ - error_report("%s: guest single-step while debugging unsupporte= d" - " (%"PRIx64", %"PRIx32")", - __func__, env->pc, debug_exit->hsr); - return false; - } - break; - case EC_AA64_BKPT: - if (kvm_find_sw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_BREAKPOINT: - if (find_hw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_WATCHPOINT: - { - CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); - if (wp) { - cs->watchpoint_hit =3D wp; - return true; - } - break; - } - default: - error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", - __func__, debug_exit->hsr, env->pc); - } - - /* If we are not handling the debug exception it must belong to - * the guest. Let's re-use the existing TCG interrupt code to set - * everything up properly. - */ - cs->exception_index =3D EXCP_BKPT; - env->exception.syndrome =3D debug_exit->hsr; - env->exception.vaddress =3D debug_exit->far; - env->exception.target_el =3D 1; - qemu_mutex_lock_iothread(); - arm_cpu_do_interrupt(cs); - qemu_mutex_unlock_iothread(); - - return false; -} --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714791374524.4217865081249; Wed, 22 Nov 2023 20:46:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YI-0006ZS-68; Wed, 22 Nov 2023 23:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xv-0006NM-4P for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:36 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xr-00068o-36 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:34 -0500 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-3b842e28917so287655b6e.1 for ; Wed, 22 Nov 2023 20:42:30 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1700714792053100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 16 ---------------- target/arm/kvm.c | 16 ++++++++++++++-- 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9fa9cb7f76..e7c32f6ed0 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -335,22 +335,6 @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); =20 -/** - * kvm_arm_get_virtual_time: - * @cs: CPUState - * - * Gets the VCPU's virtual counter and stores it in the KVM CPU state. - */ -void kvm_arm_get_virtual_time(CPUState *cs); - -/** - * kvm_arm_put_virtual_time: - * @cs: CPUState - * - * Sets the VCPU's virtual counter to the value stored in the KVM CPU stat= e. - */ -void kvm_arm_put_virtual_time(CPUState *cs); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); =20 int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 55e1b4f26e..84f300c602 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -704,7 +704,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } =20 -void kvm_arm_get_virtual_time(CPUState *cs) +/** + * kvm_arm_get_virtual_time: + * @cs: CPUState + * + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. + */ +static void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); int ret; @@ -722,7 +728,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty =3D true; } =20 -void kvm_arm_put_virtual_time(CPUState *cs) +/** + * kvm_arm_put_virtual_time: + * @cs: CPUState + * + * Sets the VCPU's virtual counter to the value stored in the KVM CPU stat= e. + */ +static void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); int ret; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714791; cv=none; d=zohomail.com; s=zohoarc; b=aQQBrUuAXyUl+Y/sPNMRyOBQ3IefzUqL9/AETk7a5x4h4Lq1TbA99F29GElczkyHDsc7aXwV9PpTE/AXoutpE43V6zRCjA0wlb1tLhghv+vnQW9iQeJYIQ8NLuh42uO9pXwRv6D++y4DZxc9NS+exAqXjM5AGp2oKzev4Dy3Brg= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 13 ------------- target/arm/kvm64.c | 7 +------ 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c32f6ed0..58c087207f 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -274,14 +274,6 @@ void kvm_arm_add_vcpu_properties(Object *obj); */ void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp); =20 -/** - * kvm_arm_steal_time_supported: - * - * Returns: true if KVM can enable steal time reporting - * and false otherwise. - */ -bool kvm_arm_steal_time_supported(void); - /** * kvm_arm_aarch32_supported: * @@ -374,11 +366,6 @@ static inline bool kvm_arm_sve_supported(void) return false; } =20 -static inline bool kvm_arm_steal_time_supported(void) -{ - return false; -} - /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6b6db9374c..fca4864b73 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -399,7 +399,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) =20 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { - bool has_steal_time =3D kvm_arm_steal_time_supported(); + bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); =20 if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { @@ -437,11 +437,6 @@ bool kvm_arm_sve_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); } =20 -bool kvm_arm_steal_time_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); -} - QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 uint32_t kvm_arm_sve_get_vls(CPUState *cs) --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714698; cv=none; d=zohomail.com; s=zohoarc; b=YKPm3QeA0/98FNrp1mGMS6SVdKYhfz6rNS8vWLvRImKnm/bxlMBBRmIiwD6fEd7jiveF9USeEdYbgDBxVXzxnlqgM6AvAgD6rPfaoorBXuiJpTJ79FlTwpoDLf/bESuhiwH86k5O6JHsK/Bw3yUO46XugChuy6vATLfIuuTV6l8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714698; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2QBUYGi1dCGuCWeKJkTo8B8CyzeEK53NkIvMTOE0ZEA=; b=IWb4/2h1X+PsGOIhkXxVaWcwf1CkYjUoH/8TFI0QmCa81uxIqYvC09qEzL0yNJvCEjC6GoeOWaHbPF52TLPM+GACbMkM0557LOVZ5M1g9QrafN3waH+ZsFcX8SW03VvuUO32cutV9JWQN6JVKJ+2Yi0bhfv3UUCEtiw/dvgtlcY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714698056411.4281739486561; Wed, 22 Nov 2023 20:44:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YI-0006ZG-0m; Wed, 22 Nov 2023 23:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xx-0006Ns-01 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:38 -0500 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xt-0006AI-DT for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:36 -0500 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3b52360cdf0so282937b6e.2 for ; Wed, 22 Nov 2023 20:42:32 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22c.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714699906100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 22 ---- target/arm/kvm.c | 265 +++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 254 ----------------------------------------- 3 files changed, 265 insertions(+), 276 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 58c087207f..e59d713973 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,28 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *= cpus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 -/** - * ARMHostCPUFeatures: information about the host CPU (identified - * by asking the host kernel) - */ -typedef struct ARMHostCPUFeatures { - ARMISARegisters isar; - uint64_t features; - uint32_t target; - const char *dtb_compatible; -} ARMHostCPUFeatures; - -/** - * kvm_arm_get_host_cpu_features: - * @ahcf: ARMHostCPUClass to fill in - * - * Probe the capabilities of the host kernel's preferred CPU and fill - * in the ARMHostCPUClass struct accordingly. - * - * Returns true on success and false otherwise. - */ -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); - /** * kvm_arm_sve_get_vls: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 84f300c602..ffe0db4293 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -41,6 +41,17 @@ static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; =20 +/** + * ARMHostCPUFeatures: information about the host CPU (identified + * by asking the host kernel) + */ +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint32_t target; + const char *dtb_compatible; +} ARMHostCPUFeatures; + static ARMHostCPUFeatures arm_host_cpu_features; =20 int kvm_arm_vcpu_init(CPUState *cs) @@ -167,6 +178,260 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + +static bool kvm_arm_pauth_supported(void) +{ + return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && + kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); +} + +static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + /* Identify the feature bits corresponding to the host CPU, and + * fill out the ARMHostCPUClass fields accordingly. To do this + * we have to create a scratch VM, create a single CPU inside it, + * and then query that CPU for the relevant ID registers. + */ + int fdarray[3]; + bool sve_supported; + bool pmu_supported =3D false; + uint64_t features =3D 0; + int err; + + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however + * we know these will only support creating one kind of guest CPU, + * which is its preferred CPU type. Fortunately these old kernels + * support only a very limited number of CPUs. + */ + static const uint32_t cpus_to_try[] =3D { + KVM_ARM_TARGET_AEM_V8, + KVM_ARM_TARGET_FOUNDATION_V8, + KVM_ARM_TARGET_CORTEX_A57, + QEMU_KVM_ARM_TARGET_NONE + }; + /* + * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() + * to use the preferred target + */ + struct kvm_vcpu_init init =3D { .target =3D -1, }; + + /* + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported =3D kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. + */ + if (kvm_arm_pauth_supported()) { + init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + if (kvm_arm_pmu_supported()) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; + pmu_supported =3D true; + } + + if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { + return false; + } + + ahcf->target =3D init.target; + ahcf->dtb_compatible =3D "arm,arm-v8"; + + err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with mini= mal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + err =3D 0; + } else { + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, + ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, + ARM64_SYS_REG(3, 0, 0, 1, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, + ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM64_SYS_REG(3, 0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM64_SYS_REG(3, 0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM64_SYS_REG(3, 0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, + ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, + ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, + ARM64_SYS_REG(3, 0, 0, 3, 6)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); + int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int ctx_cmps =3D + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version =3D 6; /* ARMv8 debug architecture */ + bool has_el3 =3D + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr =3D 0; + + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |=3D (1 << 15); /* RES1 bit */ + ahcf->isar.dbgdidr =3D dbgdidr; + } + + if (pmu_supported) { + /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + ARM64_SYS_REG(3, 3, 9, 12, 0)); + } + + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762f= cae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the V= M has + * enabled SVE support, which resulted in an error rather than= RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } + } + + kvm_arm_destroy_scratch_host_vcpu(fdarray); + + if (err < 0) { + return false; + } + + /* + * We can assume any KVM supporting CPU is at least a v8 + * with VFPv4+Neon; this in turn implies most of the other + * feature bits. + */ + features |=3D 1ULL << ARM_FEATURE_V8; + features |=3D 1ULL << ARM_FEATURE_NEON; + features |=3D 1ULL << ARM_FEATURE_AARCH64; + features |=3D 1ULL << ARM_FEATURE_PMU; + features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; + + ahcf->features =3D features; + + return true; +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index fca4864b73..504526b24c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -143,260 +143,6 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) } } =20 -static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) -{ - uint64_t ret; - struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; - int err; - - assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); - err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); - if (err < 0) { - return -1; - } - *pret =3D ret; - return 0; -} - -static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) -{ - struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; - - assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); - return ioctl(fd, KVM_GET_ONE_REG, &idreg); -} - -static bool kvm_arm_pauth_supported(void) -{ - return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && - kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); -} - -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) -{ - /* Identify the feature bits corresponding to the host CPU, and - * fill out the ARMHostCPUClass fields accordingly. To do this - * we have to create a scratch VM, create a single CPU inside it, - * and then query that CPU for the relevant ID registers. - */ - int fdarray[3]; - bool sve_supported; - bool pmu_supported =3D false; - uint64_t features =3D 0; - int err; - - /* Old kernels may not know about the PREFERRED_TARGET ioctl: however - * we know these will only support creating one kind of guest CPU, - * which is its preferred CPU type. Fortunately these old kernels - * support only a very limited number of CPUs. - */ - static const uint32_t cpus_to_try[] =3D { - KVM_ARM_TARGET_AEM_V8, - KVM_ARM_TARGET_FOUNDATION_V8, - KVM_ARM_TARGET_CORTEX_A57, - QEMU_KVM_ARM_TARGET_NONE - }; - /* - * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() - * to use the preferred target - */ - struct kvm_vcpu_init init =3D { .target =3D -1, }; - - /* - * Ask for SVE if supported, so that we can query ID_AA64ZFR0, - * which is otherwise RAZ. - */ - sve_supported =3D kvm_arm_sve_supported(); - if (sve_supported) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; - } - - /* - * Ask for Pointer Authentication if supported, so that we get - * the unsanitized field values for AA64ISAR1_EL1. - */ - if (kvm_arm_pauth_supported()) { - init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - if (kvm_arm_pmu_supported()) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; - pmu_supported =3D true; - } - - if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { - return false; - } - - ahcf->target =3D init.target; - ahcf->dtb_compatible =3D "arm,arm-v8"; - - err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); - if (unlikely(err < 0)) { - /* - * Before v4.15, the kernel only exposed a limited number of system - * registers, not including any of the interesting AArch64 ID regs. - * For the most part we could leave these fields as zero with mini= mal - * effect, since this does not affect the values seen by the guest. - * - * However, it could cause problems down the line for QEMU, - * so provide a minimal v8.0 default. - * - * ??? Could read MIDR and use knowledge from cpu64.c. - * ??? Could map a page of memory into our temp guest and - * run the tiniest of hand-crafted kernels to extract - * the values seen by the guest. - * ??? Either of these sounds like too much effort just - * to work around running a modern host kernel. - */ - ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ - err =3D 0; - } else { - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - - /* - * Note that if AArch32 support is not present in the host, - * the AArch32 sysregs are present to be read, but will - * return UNKNOWN values. This is neither better nor worse - * than skipping the reads and leaving 0, as we must avoid - * considering the values in every case. - */ - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); - - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, - ARM64_SYS_REG(3, 0, 0, 3, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, - ARM64_SYS_REG(3, 0, 0, 3, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, - ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); - - /* - * DBGDIDR is a bit complicated because the kernel doesn't - * provide an accessor for it in 64-bit mode, which is what this - * scratch VM is in, and there's no architected "64-bit sysreg - * which reads the same as the 32-bit register" the way there is - * for other ID registers. Instead we synthesize a value from the - * AArch64 ID_AA64DFR0, the same way the kernel code in - * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. - * We only do this if the CPU supports AArch32 at EL1. - */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); - int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); - int version =3D 6; /* ARMv8 debug architecture */ - bool has_el3 =3D - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); - uint32_t dbgdidr =3D 0; - - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); - dbgdidr |=3D (1 << 15); /* RES1 bit */ - ahcf->isar.dbgdidr =3D dbgdidr; - } - - if (pmu_supported) { - /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, - ARM64_SYS_REG(3, 3, 9, 12, 0)); - } - - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762f= cae - * and f81cb2c3ad41 which have a bug where the kernel doesn't - * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the V= M has - * enabled SVE support, which resulted in an error rather than= RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); - } - } - - kvm_arm_destroy_scratch_host_vcpu(fdarray); - - if (err < 0) { - return false; - } - - /* - * We can assume any KVM supporting CPU is at least a v8 - * with VFPv4+Neon; this in turn implies most of the other - * feature bits. - */ - features |=3D 1ULL << ARM_FEATURE_V8; - features |=3D 1ULL << ARM_FEATURE_NEON; - features |=3D 1ULL << ARM_FEATURE_AARCH64; - features |=3D 1ULL << ARM_FEATURE_PMU; - features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; - - ahcf->features =3D features; - - return true; -} - void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714707; cv=none; d=zohomail.com; s=zohoarc; b=erHtM4IkOBFuOW2mmU3oZdoeolPgCR5f/OYqp+HgvEzki6hOvE3n+RwyUoIYWsfYVc1tSz9fle9RJMV4f4lMtCxSvIdicCriH0CH6gmo7StPStmYUkbJlpdLW+ptxWEBXXgc2BeoL+fJ6HUMYENBePUWoWMeojBUF9/JmaFpWxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714707; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D8x3rER/p5grlbBE1M3ZzCDBILdBLJ5Jn1IStfGrw8A=; b=lMlN/iQDcYl4gCmvMhLHm4n0jsNhxxzQtlA4cy8lS7zvncozNGKlWb285xtR2zGS+lJcOSIbXWnlfqxz3qZVbDi5UCsuSuK9c1gZJPOrmYhIQp/DW0wuDDuwXZtqGfy37X5wFG5OzbYF75H7lAsTRbvvvOF17Bs53cHr/3sq4Bc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714707422559.0588859757657; Wed, 22 Nov 2023 20:45:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YI-0006aH-Qf; Wed, 22 Nov 2023 23:42:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Xy-0006O6-Uk for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:44 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xv-0006BK-3Z for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:37 -0500 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-3b833b54f14so252086b6e.1 for ; Wed, 22 Nov 2023 20:42:34 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714552; x=1701319352; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D8x3rER/p5grlbBE1M3ZzCDBILdBLJ5Jn1IStfGrw8A=; b=ajaaqxi503q8pxrYvS4AjHyPuoE+xRdCE6cg3oak8rIU0/rtj4lwHvnyPjEtMHmn/v um3P3/aTYQnG+PFGKPm6ZD73zENr/Qm+GTrJWNGdC4rjN/+vj+LRMHNYw/PCqcrfhdR1 4Znc9Ftf3YhmZPKRhtq7WENMLjkYiRDrsCjQ2uJcs2OOk+gnorx2yQS/6D57fD9/KBOD c9RsZCznKhJ33yFs/yaPLAo6/lea5nS6gpgmv8L1g2CcOKtOfEgeIx0CtFTrbaVi+t7+ JPa4uyNFovZ4kkXwZft38KLYKVryiVnhrYo8OrfSrvbpyT0bdwMy5KFNHbiIrjxHHKmW zmCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714552; x=1701319352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D8x3rER/p5grlbBE1M3ZzCDBILdBLJ5Jn1IStfGrw8A=; b=uqzbWVcxLpotnpBsV7FafD8VMdc2cBovOsqegFt0ZGIMLnHIdOC9PT0YEABerM6CPQ UAgoHdUk6sOIvvWSCuLZb4fMu3Zs9gNdJqH1BOXcmtsKbC/kevrjBOAKP93hr+Us/vcU BLY9/f/8Cpa6q6DBRLyWEtsXMfmwqVjEjCxBSM3EpETxW6VLmIJ70CsbeT3lhF0TrtZ0 wpDfcHL6oAIoYf4A+7n12kSmYraUCy1vJ9fF4H5/eUTaeAFLWgw0CAfFVsk5a9ZhWga8 skw/s2Fb++pq2qHOOVanEpMpL8O3h/Ez/bhG3HtFqPI4FThZa+/9oB4UHE9Scml7XjwB lvxg== X-Gm-Message-State: AOJu0YxPC8Z0b1dCb9vaVaGwoZhBSU/XGBh7DwzYQq8uNzSMag9We2LW Vo1DcUgBECdMbmzEodtlc86hUK1s9SDJ4c4iafX+r81A X-Google-Smtp-Source: AGHT+IF84xmWckQIK42u0YDdssY1cVTe633BMv2RbLEp2i3TaJ2XDPrix6BuNm6UknMVV1PnSv2TUA== X-Received: by 2002:a05:6808:13d3:b0:3b2:e4b7:2af2 with SMTP id d19-20020a05680813d300b003b2e4b72af2mr857720oiw.6.1700714552738; Wed, 22 Nov 2023 20:42:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 11/21] target/arm/kvm: Use a switch for kvm_arm_cpreg_level Date: Wed, 22 Nov 2023 22:42:09 -0600 Message-Id: <20231123044219.896776-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714707889100001 Content-Type: text/plain; charset="utf-8" Use a switch instead of a linear search through data. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm64.c | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 504526b24c..61fb9dbde0 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,32 +361,18 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } =20 -typedef struct CPRegStateLevel { - uint64_t regidx; - int level; -} CPRegStateLevel; - -/* All system registers not listed in the following table are assumed to be - * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less - * often, you must add it to this table with a state of either - * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ -static const CPRegStateLevel non_runtime_cpregs[] =3D { - { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE }, - { KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE }, -}; - int kvm_arm_cpreg_level(uint64_t regidx) { - int i; - - for (i =3D 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) { - const CPRegStateLevel *l =3D &non_runtime_cpregs[i]; - if (l->regidx =3D=3D regidx) { - return l->level; - } + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; } - return KVM_PUT_RUNTIME_STATE; } =20 --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714688; cv=none; d=zohomail.com; s=zohoarc; b=bnyUE4JoANYBx6GsWlzZlAOrEfetGhUE2SOIHugcpS6vl6wWkIWarm+iMuCFbxtzndNsMEN+oMwgDR660opzyWIbKhhAmJYeyG2gXbNjZJ0jOh3IhxcutxSciavbNdgJ+Biox1ze50r6GgGZVSDqCBj8GLi/Hk+c8Lp5DVPVs30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714688; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=f0csjBzUKQmzo27GffQhvUdSife+3bvwrwa84N7+vIM=; b=emPfWrCZmDenTTWgkcZ6BkneQbMSMmiGD17MNLn4NJ2iOrQ/G22BXMD8hOwh/ftkf05BYhDXb1KgNB8pgFfc9HVA//WEFwGJPSe9G2beRScYS6BMEGJwYax2I2bBAhPKSJHOZV509xQYelFyF6j1IbgRk3URfQpQf1h7Obdr4wA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714688889591.0617273801894; Wed, 22 Nov 2023 20:44:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YJ-0006bF-RI; Wed, 22 Nov 2023 23:42:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y0-0006OM-T3 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:44 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xw-0006BL-MM for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:39 -0500 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3b833b54f14so252090b6e.1 for ; Wed, 22 Nov 2023 20:42:34 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714554; x=1701319354; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f0csjBzUKQmzo27GffQhvUdSife+3bvwrwa84N7+vIM=; b=S6Gx1+McceoIk4xJkUX9rJm41OLdLbr8Ra+QlV8LBa9+1VYWHLZQ2XsJz1my2+FfjA lEYabSfnFF0kRs08JDghCpi1bq4gJ2RwNUSC9fVCadQLpV1qrOfWFqNrPKjXLowaYlNB EAg99865AXp33esyj6l+jM96vXGvVnjgptAjlqEondHjdQTzFmpCNPrJUZpxxuXgkvex 8PYlsd3mzGw5uXUrkLkttC0kKsrsg+u/2HRslWmj+TMBtuJ4eKjWmu/n4sNhoCiKRef/ Vv/dSdZhpqDQ77YNmM46FbMitQx6ygcXcDcn8dQzc6cbrkN8ohZ0BqRDgONEf3j2DHKX 9QFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714554; x=1701319354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f0csjBzUKQmzo27GffQhvUdSife+3bvwrwa84N7+vIM=; b=OhQ8CiBCwWeKiDZLtgT+jpud8tGFcrb3Xo5yDv1Sk1hIWYEQ8eM1Uj3+Op8Mk7WGdv Wv4Cclt8wA0PEmWEAhhQ/RjlYU7Hsn/Lad3Vi1idz8YrHO7B80GvUlgRfggZjrmntVTf xhi5H0kYoRF5i8UOZXCeTXj5KPfk4N4m9U6FwO0J5CLH+46ESoGpd5Ov0BkdJqGD94vC rfzHtQdHyaZesxHtzaeR9sP/ROvyKujVa6IFX9LI4XbUPmMWytJtzpG7OHzcAiZLTtg/ IhHCmOl4o2CtpxQBDAFJVexvfuJe2Awhw0BmPSJp5NADwUMp18hGJvE7I09l5kYQyLTe pqmQ== X-Gm-Message-State: AOJu0YwFPzgAUqCseimGlnJrzYIYA9Y0ytaeVBKyjuj4GzH0VCJ188AF M3Klv8lwLjw4UZKftQWVHJsfBGGYJ/ORgoQd7ytDtEVx X-Google-Smtp-Source: AGHT+IGLTW6sUtdYxtg5W/TrdgDCCTKef+jrfrOq0qByrCS/RqelizPPFZHGQTkC2Q+oYxLqwXyzLw== X-Received: by 2002:a05:6808:f92:b0:3b8:33d1:806d with SMTP id o18-20020a0568080f9200b003b833d1806dmr736999oiw.22.1700714553754; Wed, 22 Nov 2023 20:42:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 12/21] target/arm/kvm: Move kvm_arm_cpreg_level and unexport Date: Wed, 22 Nov 2023 22:42:10 -0600 Message-Id: <20231123044219.896776-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714689774100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 9 --------- target/arm/kvm.c | 22 ++++++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 22 insertions(+), 24 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e59d713973..2755ee8366 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -87,15 +87,6 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); */ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); =20 -/** - * kvm_arm_cpreg_level: - * @regidx: KVM register index - * - * Return the level of this coprocessor/system register. Return value is - * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STAT= E. - */ -int kvm_arm_cpreg_level(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ffe0db4293..dadc3fd755 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -817,6 +817,28 @@ out: return ret; } =20 +/** + * kvm_arm_cpreg_level: + * @regidx: KVM register index + * + * Return the level of this coprocessor/system register. Return value is + * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STAT= E. + */ +static int kvm_arm_cpreg_level(uint64_t regidx) +{ + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; + } + return KVM_PUT_RUNTIME_STATE; +} + bool write_kvmstate_to_list(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 61fb9dbde0..a184cca4dc 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,21 +361,6 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } =20 -int kvm_arm_cpreg_level(uint64_t regidx) -{ - /* - * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. - * If a register should be written less often, you must add it here - * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ - switch (regidx) { - case KVM_REG_ARM_TIMER_CNT: - case KVM_REG_ARM_PTIMER_CNT: - return KVM_PUT_FULL_STATE; - } - return KVM_PUT_RUNTIME_STATE; -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714676; cv=none; d=zohomail.com; s=zohoarc; b=dOJuD+5otnulsIK8FX/2qQ1+D+zOpaSp6yDmuQNL+UuVVOeOj7+A/Ab75iDSRW93Am9RvLL9lapxC0v48nDdgpYlI530UGKY2+QKU3s5PvY4pDDtvfsww8CP2BqDMzwc7Njk7l6I+HOY48a/DtLaCdIqabe7ibpkmvLgmFC10Dc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714676; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sKoFS6vupvdOb9gSEJ//vdL16AVl5a0a1fSx8jeXTzw=; b=OgBHTXU1psGO6vsza+7Wkr//xHzdK0mSF1oJLcZ40eRaTFn49q9BkxOeqkrdXjnzL4RTcYTQ4vjrIQXuGy3u3g5dwp5w0vzDzcDy/tembLPkoKCYaJfNA63IpAjfN5/2AV1StumY3VN/ZrFrtWtwK5iVqxxYDosRvYMBULYMao4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714676224740.6291512438559; Wed, 22 Nov 2023 20:44:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YM-0006dV-Ej; Wed, 22 Nov 2023 23:43:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y2-0006OQ-Hg for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:44 -0500 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Xw-0006CD-Ny for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:41 -0500 Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3b83432ca31so365782b6e.1 for ; Wed, 22 Nov 2023 20:42:36 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714554; x=1701319354; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sKoFS6vupvdOb9gSEJ//vdL16AVl5a0a1fSx8jeXTzw=; b=aYZ7ACcy0X2wpyy1XPWRSKVvHEMCQJqc3ACbQ12cG1lcZ4qxMxD0G3Xcu+rq7awOrK LqIWBsWQ9bU4DnyxAaxFRX9sfdGZ2W4a5RiifId1MRE8VDDiofpYGP00rLk3HPUBOYZp 0TEZd+Zb0wpIPwIHPvBOmYNXXwIhCJZ4eonWZ0ukrR7BO6Xg3Vqv7j20vKr0t+tiwi+5 kS0s1HLE7I5NNQMV//fwdBGYpCQt91PaY4SJFaX21Vk1ZKH5BJs+a8jytvUHWQHTN0qN QqoyNnzrTqDGIYDJVs/Z8ZnCgDOwEp01hlTY8BXp74xMj++umU47I4uCXk2XDEq0QH0A 7jgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714554; x=1701319354; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714677784100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 23 +++++++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 23 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2755ee8366..1043123cc7 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -77,16 +77,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t = devid, uint64_t group, */ int kvm_arm_init_cpreg_list(ARMCPU *cpu); =20 -/** - * kvm_arm_reg_syncs_via_cpreg_list: - * @regidx: KVM register index - * - * Return true if this KVM register should be synchronized via the - * cpreg list of arbitrary system registers, false if it is synchronized - * by hand using code in kvm_arch_get/put_registers(). - */ -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index dadc3fd755..9bca6baf35 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -740,6 +740,29 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 +/** + * kvm_arm_reg_syncs_via_cpreg_list: + * @regidx: KVM register index + * + * Return true if this KVM register should be synchronized via the + * cpreg list of arbitrary system registers, false if it is synchronized + * by hand using code in kvm_arch_get/put_registers(). + */ +static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) +{ + /* Return true if the regidx is a register we should synchronize + * via the cpreg_tuples array (ie is not a core or sve reg that + * we sync by hand in kvm_arch_get/put_registers()) + */ + switch (regidx & KVM_REG_ARM_COPROC_MASK) { + case KVM_REG_ARM_CORE: + case KVM_REG_ARM64_SVE: + return false; + default: + return true; + } +} + /* Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index a184cca4dc..52c0a6d3af 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -346,21 +346,6 @@ int kvm_arch_destroy_vcpu(CPUState *cs) return 0; } =20 -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) -{ - /* Return true if the regidx is a register we should synchronize - * via the cpreg_tuples array (ie is not a core or sve reg that - * we sync by hand in kvm_arch_get/put_registers()) - */ - switch (regidx & KVM_REG_ARM_COPROC_MASK) { - case KVM_REG_ARM_CORE: - case KVM_REG_ARM64_SVE: - return false; - default: - return true; - } -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714556; x=1701319356; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8lCxf3dNn8P24IkX9Y+wMxHodiJIeqj1vGg6wXycsss=; b=w3BJFDv1e0eP1y3cVEj2rXAb0EOVHCmYLypE+/6LRr+GSNf0bK4NxJxvzlgO0kvzaY ZJWUlSxvTqNMwEZx4NbWGS9faFc1tpS3NLUhJ4bwv0NVtASYjJyiYF4OaQwSy1+DzugD sr4US0sMgjEZG/SMxQIJYZ38UvgWUDgNnl8zl93m4+CeIOqWOSHpmuLcxMqahh2dVn7F XDBpR7IgIy+C0QIAJTi0plphKj57nUfBqkQoF9I0ngdNo2RVaJLataLougwqlzcUyQUq RWH964mh8Z1Mvb7ccdqi8MCyAMteYeFoHv4b8hZZFsUllwJlYGbb60okR0J7eZx8wdLp 307w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714556; x=1701319356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8lCxf3dNn8P24IkX9Y+wMxHodiJIeqj1vGg6wXycsss=; b=uvzQgf+ohs81Le/X4v1qhZGRV4NzTDm/+ssQ5G41AH2VHfjsw8OdO41d0g9Shx8vm2 ZOIXAe0qmrMGev3FYuVQcufRcFtfNRjWCafCq3vggSP7lUifDwkkQsGNBJ5RS/Gmt4Fj BIBocPpmUBBaKY+bFsqX38Wv7RNIq6ciDPlDRcaDswf0wwyS2jnyMITeixriVOi4lbTU OAdw7frFnE2vjvYLGlNLo3JgShJz1af4vU02C3dsEmFGx1T9auViUpfAKezCN8zz02uB GCiBPxJBYhA/xfp62PUxoUHkBm4fx6lgpElp4YZO29pOmsTxnfazmvZG1cuve2oqDZLw JDUA== X-Gm-Message-State: AOJu0YwDnGBNoGl2v83njl1U6h2NFgHByS99Be11HLNMjAz8DyKgN/oZ s9+jRMIZ6lbga9APnpjgVeCKvpQY6DSMobCElGEJALcZ X-Google-Smtp-Source: AGHT+IEwEGmJn5+04G1cucsOvAurnYOj1QJGnENDk+hdzRkHXMij0+zDyCUvJ70Z8lEmlimUnjVroQ== X-Received: by 2002:a05:6808:18a8:b0:3b8:3fce:5fc3 with SMTP id bi40-20020a05680818a800b003b83fce5fc3mr4468439oib.33.1700714556270; Wed, 22 Nov 2023 20:42:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 14/21] target/arm/kvm: Merge kvm64.c into kvm.c Date: Wed, 22 Nov 2023 22:42:12 -0600 Message-Id: <20231123044219.896776-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714625822100003 Since kvm32.c was removed, there is no need to keep them separate. This will allow more symbols to be unexported. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm.c | 789 +++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 820 ----------------------------------------- target/arm/meson.build | 2 +- 3 files changed, 790 insertions(+), 821 deletions(-) delete mode 100644 target/arm/kvm64.c diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9bca6baf35..466b848156 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -19,6 +19,7 @@ #include "qom/object.h" #include "qapi/error.h" #include "sysemu/sysemu.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -28,10 +29,13 @@ #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" +#include "exec/gdbstub.h" #include "hw/boards.h" #include "hw/irq.h" #include "qapi/visitor.h" #include "qemu/log.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/ghes.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO @@ -1614,3 +1618,788 @@ void kvm_arch_accel_class_init(ObjectClass *oc) object_class_property_set_description(oc, "eager-split-size", "Eager Page Split chunk size for hugepages. (default: 0, disabled)= "); } + +int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return insert_hw_breakpoint(addr); + break; + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return insert_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return delete_hw_breakpoint(addr); + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return delete_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +void kvm_arch_remove_all_hw_breakpoints(void) +{ + if (cur_hw_wps > 0) { + g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); + } + if (cur_hw_bps > 0) { + g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); + } +} + +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, + const char *name) +{ + int err; + + err =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); + if (err !=3D 0) { + error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + err =3D kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); + if (err !=3D 0) { + error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + return true; +} + +void kvm_arm_pmu_init(CPUState *cs) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, + .attr =3D KVM_ARM_VCPU_PMU_V3_INIT, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to init PMU"); + abort(); + } +} + +void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, + .addr =3D (intptr_t)&irq, + .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to set irq for PMU"); + abort(); + } +} + +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PVTIME_CTRL, + .attr =3D KVM_ARM_VCPU_PVTIME_IPA, + .addr =3D (uint64_t)&ipa, + }; + + if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { + error_report("failed to init PVTIME IPA"); + abort(); + } +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); + + if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { + if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { + cpu->kvm_steal_time =3D ON_OFF_AUTO_OFF; + } else { + cpu->kvm_steal_time =3D ON_OFF_AUTO_ON; + } + } else if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_ON) { + if (!has_steal_time) { + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "on this host"); + return; + } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* + * DEN0057A chapter 2 says "This specification only covers + * systems in which the Execution state of the hypervisor + * as well as EL1 of virtual machines is AArch64.". And, + * to ensure that, the smc/hvc calls are only specified as + * smc64/hvc64. + */ + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "for AArch32 guests"); + return; + } + } +} + +bool kvm_arm_aarch32_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); +} + +bool kvm_arm_sve_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); +} + +QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); + +uint32_t kvm_arm_sve_get_vls(CPUState *cs) +{ + /* Only call this function if kvm_arm_sve_supported() returns true. */ + static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; + static bool probed; + uint32_t vq =3D 0; + int i; + + /* + * KVM ensures all host CPUs support the same set of vector lengths. + * So we only need to create the scratch VCPUs once and then cache + * the results. + */ + if (!probed) { + struct kvm_vcpu_init init =3D { + .target =3D -1, + .features[0] =3D (1 << KVM_ARM_VCPU_SVE), + }; + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM64_SVE_VLS, + .addr =3D (uint64_t)&vls[0], + }; + int fdarray[3], ret; + + probed =3D true; + + if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { + error_report("failed to create scratch VCPU with SVE enabled"); + abort(); + } + ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, ®); + kvm_arm_destroy_scratch_host_vcpu(fdarray); + if (ret) { + error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", + strerror(errno)); + abort(); + } + + for (i =3D KVM_ARM64_SVE_VLS_WORDS - 1; i >=3D 0; --i) { + if (vls[i]) { + vq =3D 64 - clz64(vls[i]) + i * 64; + break; + } + } + if (vq > ARM_MAX_VQ) { + warn_report("KVM supports vector lengths larger than " + "QEMU can enable"); + vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + } + } + + return vls[0]; +} + +static int kvm_arm_sve_set_vls(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; + + assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); + + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); +} + +#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + +int kvm_arch_init_vcpu(CPUState *cs) +{ + int ret; + uint64_t mpidr; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t psciver; + + if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || + !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + error_report("KVM is not supported for this guest CPU type"); + return -EINVAL; + } + + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + + /* Determine init features for this CPU */ + memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); + if (cs->start_powered_off) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_POWER_OFF; + } + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { + cpu->psci_version =3D QEMU_PSCI_VERSION_0_2; + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PSCI_0_2; + } + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_EL1_32BIT; + } + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { + cpu->has_pmu =3D false; + } + if (cpu->has_pmu) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; + } else { + env->features &=3D ~(1ULL << ARM_FEATURE_PMU); + } + if (cpu_isar_feature(aa64_sve, cpu)) { + assert(kvm_arm_sve_supported()); + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_SVE; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + /* Do KVM_ARM_VCPU_INIT ioctl */ + ret =3D kvm_arm_vcpu_init(cs); + if (ret) { + return ret; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arm_sve_set_vls(cs); + if (ret) { + return ret; + } + ret =3D kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); + if (ret) { + return ret; + } + } + + /* + * KVM reports the exact PSCI version it is implementing via a + * special sysreg. If it is present, use its contents to determine + * what to report to the guest in the dtb (it is the PSCI version, + * in the same 15-bits major 16-bits minor format that PSCI_VERSION + * returns). + */ + if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { + cpu->psci_version =3D psciver; + } + + /* + * When KVM is in use, PSCI is emulated in-kernel and not by qemu. + * Currently KVM has its own idea about MPIDR assignment, so we + * override our defaults with what we get from KVM. + */ + ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); + if (ret) { + return ret; + } + cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; + + /* Check whether user space can specify guest syndrome value */ + kvm_arm_init_serror_injection(cs); + + return kvm_arm_init_cpreg_list(cpu); +} + +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + +/* Callers must hold the iothread mutex lock */ +static void kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu =3D ARM_CPU(c); + CPUARMState *env =3D &cpu->env; + uint32_t esr; + bool same_el; + + c->exception_index =3D EXCP_DATA_ABORT; + env->exception.target_el =3D 1; + + /* + * Set the DFSC to synchronous external abort and set FnV to not valid, + * this will tell guest the FAR_ELx is UNKNOWN for this abort. + */ + same_el =3D arm_current_el(env) =3D=3D env->exception.target_el; + esr =3D syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); + + env->exception.syndrome =3D esr; + + arm_cpu_do_interrupt(c); +} + +#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +static int kvm_arch_put_fpsimd(CPUState *cs) +{ + CPUARMState *env =3D &ARM_CPU(cs)->env; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); +#if HOST_BIG_ENDIAN + uint64_t fp_val[2] =3D { q[1], q[0] }; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), + fp_val); +#else + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); +#endif + if (ret) { + return ret; + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard + * code the slice index to zero for now as it's unlikely we'll need more t= han + * one slice for quite some time. + */ +static int kvm_arch_put_sve(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t tmp[ARM_MAX_VQ * 2]; + uint64_t *r; + int n, ret; + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + } + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + } + + r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + + return 0; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + uint64_t val; + uint32_t fpr; + int i, ret; + unsigned int el; + + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* If we are in AArch32 mode then we need to copy the AArch32 regs to = the + * AArch64 registers before pushing them out to 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_32_to_64(env); + } + + for (i =3D 0; i < 31; i++) { + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_save_sp(env, 1); + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ + if (is_a64(env)) { + val =3D pstate_read(env); + } else { + val =3D cpsr_read(env); + } + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); + if (ret) { + return ret; + } + + /* Saved Program State Registers + * + * Before we restore from the banked_spsr[] array we need to + * ensure that any modifications to env->spsr are correctly + * reflected in the banks. + */ + el =3D arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i =3D bank_number(env->uncached_cpsr & CPSR_M); + env->banked_spsr[i] =3D env->spsr; + } + + /* KVM 0-4 map to QEMU banks 1-5 */ + for (i =3D 0; i < KVM_NR_SPSR; i++) { + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arch_put_sve(cs); + } else { + ret =3D kvm_arch_put_fpsimd(cs); + } + if (ret) { + return ret; + } + + fpr =3D vfp_get_fpsr(env); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + + fpr =3D vfp_get_fpcr(env); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + + write_cpustate_to_list(cpu, true); + + if (!write_list_to_kvmstate(cpu, level)) { + return -EINVAL; + } + + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret =3D kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + + kvm_arm_sync_mpstate_to_kvm(cpu); + + return ret; +} + +static int kvm_arch_get_fpsimd(CPUState *cs) +{ + CPUARMState *env =3D &ARM_CPU(cs)->env; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); + if (ret) { + return ret; + } else { +#if HOST_BIG_ENDIAN + uint64_t t; + t =3D q[0], q[0] =3D q[1], q[1] =3D t; +#endif + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard + * code the slice index to zero for now as it's unlikely we'll need more t= han + * one slice for quite some time. + */ +static int kvm_arch_get_sve(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t *r; + int n, ret; + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r =3D &env->vfp.zregs[n].d[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, cpu->sve_max_vq * 2); + } + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r =3D &env->vfp.pregs[n].p[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + } + + r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + + return 0; +} + +int kvm_arch_get_registers(CPUState *cs) +{ + uint64_t val; + unsigned int el; + uint32_t fpr; + int i, ret; + + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + for (i =3D 0; i < 31; i++) { + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + if (is_a64(env)) { + pstate_write(env, val); + } else { + cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_restore_sp(env, 1); + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + /* If we are in AArch32 mode then we need to sync the AArch32 regs wit= h the + * incoming AArch64 regs received from 64-bit KVM. + * We must perform this after all of the registers have been acquired = from + * the kernel. + */ + if (!is_a64(env)) { + aarch64_sync_64_to_32(env); + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); + if (ret) { + return ret; + } + + /* Fetch the SPSR registers + * + * KVM SPSRs 0-4 map to QEMU banks 1-5 + */ + for (i =3D 0; i < KVM_NR_SPSR; i++) { + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + el =3D arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i =3D bank_number(env->uncached_cpsr & CPSR_M); + env->spsr =3D env->banked_spsr[i]; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arch_get_sve(cs); + } else { + ret =3D kvm_arch_get_fpsimd(cs); + } + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpsr(env, fpr); + + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpcr(env, fpr); + + ret =3D kvm_get_vcpu_events(cpu); + if (ret) { + return ret; + } + + if (!write_kvmstate_to_list(cpu)) { + return -EINVAL; + } + /* Note that it's OK to have registers which aren't in CPUState, + * so we can ignore a failure return here. + */ + write_list_to_cpustate(cpu); + + kvm_arm_sync_mpstate_to_qemu(cpu); + + /* TODO: other registers */ + return ret; +} + +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); + + if (acpi_ghes_present() && addr) { + ram_addr =3D qemu_ram_addr_from_host(addr); + if (ram_addr !=3D RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { + kvm_hwpoison_page_add(ram_addr); + /* + * If this is a BUS_MCEERR_AR, we know we have been called + * synchronously from the vCPU thread, so we can easily + * synchronize the state and inject an error. + * + * TODO: we currently don't tell the guest at all about + * BUS_MCEERR_AO. In that case we might either be being + * called synchronously from the vCPU thread, or a bit + * later from the main thread, so doing the injection of + * the error would be more complicated. + */ + if (code =3D=3D BUS_MCEERR_AR) { + kvm_cpu_synchronize_state(c); + if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr))= { + kvm_inject_arm_sea(c); + } else { + error_report("failed to record the error"); + abort(); + } + } + return; + } + if (code =3D=3D BUS_MCEERR_AO) { + error_report("Hardware memory error at addr %p for memory used= by " + "QEMU itself instead of guest system!", addr); + } + } + + if (code =3D=3D BUS_MCEERR_AR) { + error_report("Hardware memory error!"); + exit(1); + } +} + +/* C6.6.29 BRK instruction */ +static const uint32_t brk_insn =3D 0xd4200000; + +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) +{ + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { + return -EINVAL; + } + return 0; +} + +int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) +{ + static uint32_t brk; + + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk !=3D brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { + return -EINVAL; + } + return 0; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c deleted file mode 100644 index 52c0a6d3af..0000000000 --- a/target/arm/kvm64.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * ARM implementation of KVM hooks, 64 bit specific code - * - * Copyright Mian-M. Hamayun 2013, Virtual Open Systems - * Copyright Alex Benn=C3=A9e 2014, Linaro - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include -#include - -#include -#include - -#include "qapi/error.h" -#include "cpu.h" -#include "qemu/timer.h" -#include "qemu/error-report.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "exec/gdbstub.h" -#include "sysemu/runstate.h" -#include "sysemu/kvm.h" -#include "sysemu/kvm_int.h" -#include "kvm_arm.h" -#include "internals.h" -#include "cpu-features.h" -#include "hw/acpi/acpi.h" -#include "hw/acpi/ghes.h" - - -int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return insert_hw_breakpoint(addr); - break; - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return insert_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - -int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return delete_hw_breakpoint(addr); - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return delete_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - - -void kvm_arch_remove_all_hw_breakpoints(void) -{ - if (cur_hw_wps > 0) { - g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); - } - if (cur_hw_bps > 0) { - g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); - } -} - -static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, - const char *name) -{ - int err; - - err =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); - if (err !=3D 0) { - error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - err =3D kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); - if (err !=3D 0) { - error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - return true; -} - -void kvm_arm_pmu_init(CPUState *cs) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, - .attr =3D KVM_ARM_VCPU_PMU_V3_INIT, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to init PMU"); - abort(); - } -} - -void kvm_arm_pmu_set_irq(CPUState *cs, int irq) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, - .addr =3D (intptr_t)&irq, - .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to set irq for PMU"); - abort(); - } -} - -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PVTIME_CTRL, - .attr =3D KVM_ARM_VCPU_PVTIME_IPA, - .addr =3D (uint64_t)&ipa, - }; - - if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { - error_report("failed to init PVTIME IPA"); - abort(); - } -} - -void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); - - if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { - if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { - cpu->kvm_steal_time =3D ON_OFF_AUTO_OFF; - } else { - cpu->kvm_steal_time =3D ON_OFF_AUTO_ON; - } - } else if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_ON) { - if (!has_steal_time) { - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "on this host"); - return; - } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - /* - * DEN0057A chapter 2 says "This specification only covers - * systems in which the Execution state of the hypervisor - * as well as EL1 of virtual machines is AArch64.". And, - * to ensure that, the smc/hvc calls are only specified as - * smc64/hvc64. - */ - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "for AArch32 guests"); - return; - } - } -} - -bool kvm_arm_aarch32_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); -} - -bool kvm_arm_sve_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); -} - -QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); - -uint32_t kvm_arm_sve_get_vls(CPUState *cs) -{ - /* Only call this function if kvm_arm_sve_supported() returns true. */ - static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; - static bool probed; - uint32_t vq =3D 0; - int i; - - /* - * KVM ensures all host CPUs support the same set of vector lengths. - * So we only need to create the scratch VCPUs once and then cache - * the results. - */ - if (!probed) { - struct kvm_vcpu_init init =3D { - .target =3D -1, - .features[0] =3D (1 << KVM_ARM_VCPU_SVE), - }; - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM64_SVE_VLS, - .addr =3D (uint64_t)&vls[0], - }; - int fdarray[3], ret; - - probed =3D true; - - if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { - error_report("failed to create scratch VCPU with SVE enabled"); - abort(); - } - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, ®); - kvm_arm_destroy_scratch_host_vcpu(fdarray); - if (ret) { - error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", - strerror(errno)); - abort(); - } - - for (i =3D KVM_ARM64_SVE_VLS_WORDS - 1; i >=3D 0; --i) { - if (vls[i]) { - vq =3D 64 - clz64(vls[i]) + i * 64; - break; - } - } - if (vq > ARM_MAX_VQ) { - warn_report("KVM supports vector lengths larger than " - "QEMU can enable"); - vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - } - } - - return vls[0]; -} - -static int kvm_arm_sve_set_vls(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; - - assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); - - return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); -} - -#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 - -int kvm_arch_init_vcpu(CPUState *cs) -{ - int ret; - uint64_t mpidr; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t psciver; - - if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { - error_report("KVM is not supported for this guest CPU type"); - return -EINVAL; - } - - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); - - /* Determine init features for this CPU */ - memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); - if (cs->start_powered_off) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_POWER_OFF; - } - if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { - cpu->psci_version =3D QEMU_PSCI_VERSION_0_2; - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PSCI_0_2; - } - if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_EL1_32BIT; - } - if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { - cpu->has_pmu =3D false; - } - if (cpu->has_pmu) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; - } else { - env->features &=3D ~(1ULL << ARM_FEATURE_PMU); - } - if (cpu_isar_feature(aa64_sve, cpu)) { - assert(kvm_arm_sve_supported()); - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_SVE; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - /* Do KVM_ARM_VCPU_INIT ioctl */ - ret =3D kvm_arm_vcpu_init(cs); - if (ret) { - return ret; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arm_sve_set_vls(cs); - if (ret) { - return ret; - } - ret =3D kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); - if (ret) { - return ret; - } - } - - /* - * KVM reports the exact PSCI version it is implementing via a - * special sysreg. If it is present, use its contents to determine - * what to report to the guest in the dtb (it is the PSCI version, - * in the same 15-bits major 16-bits minor format that PSCI_VERSION - * returns). - */ - if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { - cpu->psci_version =3D psciver; - } - - /* - * When KVM is in use, PSCI is emulated in-kernel and not by qemu. - * Currently KVM has its own idea about MPIDR assignment, so we - * override our defaults with what we get from KVM. - */ - ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); - if (ret) { - return ret; - } - cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; - - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - - return kvm_arm_init_cpreg_list(cpu); -} - -int kvm_arch_destroy_vcpu(CPUState *cs) -{ - return 0; -} - -/* Callers must hold the iothread mutex lock */ -static void kvm_inject_arm_sea(CPUState *c) -{ - ARMCPU *cpu =3D ARM_CPU(c); - CPUARMState *env =3D &cpu->env; - uint32_t esr; - bool same_el; - - c->exception_index =3D EXCP_DATA_ABORT; - env->exception.target_el =3D 1; - - /* - * Set the DFSC to synchronous external abort and set FnV to not valid, - * this will tell guest the FAR_ELx is UNKNOWN for this abort. - */ - same_el =3D arm_current_el(env) =3D=3D env->exception.target_el; - esr =3D syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); - - env->exception.syndrome =3D esr; - - arm_cpu_do_interrupt(c); -} - -#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -static int kvm_arch_put_fpsimd(CPUState *cs) -{ - CPUARMState *env =3D &ARM_CPU(cs)->env; - int i, ret; - - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); -#if HOST_BIG_ENDIAN - uint64_t fp_val[2] =3D { q[1], q[0] }; - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), - fp_val); -#else - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); -#endif - if (ret) { - return ret; - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard - * code the slice index to zero for now as it's unlikely we'll need more t= han - * one slice for quite some time. - */ -static int kvm_arch_put_sve(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t tmp[ARM_MAX_VQ * 2]; - uint64_t *r; - int n, ret; - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - } - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - } - - r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - - return 0; -} - -int kvm_arch_put_registers(CPUState *cs, int level) -{ - uint64_t val; - uint32_t fpr; - int i, ret; - unsigned int el; - - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* If we are in AArch32 mode then we need to copy the AArch32 regs to = the - * AArch64 registers before pushing them out to 64-bit KVM. - */ - if (!is_a64(env)) { - aarch64_sync_32_to_64(env); - } - - for (i =3D 0; i < 31; i++) { - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_save_sp(env, 1); - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ - if (is_a64(env)) { - val =3D pstate_read(env); - } else { - val =3D cpsr_read(env); - } - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); - if (ret) { - return ret; - } - - /* Saved Program State Registers - * - * Before we restore from the banked_spsr[] array we need to - * ensure that any modifications to env->spsr are correctly - * reflected in the banks. - */ - el =3D arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i =3D bank_number(env->uncached_cpsr & CPSR_M); - env->banked_spsr[i] =3D env->spsr; - } - - /* KVM 0-4 map to QEMU banks 1-5 */ - for (i =3D 0; i < KVM_NR_SPSR; i++) { - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arch_put_sve(cs); - } else { - ret =3D kvm_arch_put_fpsimd(cs); - } - if (ret) { - return ret; - } - - fpr =3D vfp_get_fpsr(env); - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - - fpr =3D vfp_get_fpcr(env); - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - - write_cpustate_to_list(cpu, true); - - if (!write_list_to_kvmstate(cpu, level)) { - return -EINVAL; - } - - /* - * Setting VCPU events should be triggered after syncing the registers - * to avoid overwriting potential changes made by KVM upon calling - * KVM_SET_VCPU_EVENTS ioctl - */ - ret =3D kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; -} - -static int kvm_arch_get_fpsimd(CPUState *cs) -{ - CPUARMState *env =3D &ARM_CPU(cs)->env; - int i, ret; - - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); - if (ret) { - return ret; - } else { -#if HOST_BIG_ENDIAN - uint64_t t; - t =3D q[0], q[0] =3D q[1], q[1] =3D t; -#endif - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard - * code the slice index to zero for now as it's unlikely we'll need more t= han - * one slice for quite some time. - */ -static int kvm_arch_get_sve(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t *r; - int n, ret; - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r =3D &env->vfp.zregs[n].d[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, cpu->sve_max_vq * 2); - } - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r =3D &env->vfp.pregs[n].p[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - } - - r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - - return 0; -} - -int kvm_arch_get_registers(CPUState *cs) -{ - uint64_t val; - unsigned int el; - uint32_t fpr; - int i, ret; - - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - for (i =3D 0; i < 31; i++) { - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); - if (is_a64(env)) { - pstate_write(env, val); - } else { - cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_restore_sp(env, 1); - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - /* If we are in AArch32 mode then we need to sync the AArch32 regs wit= h the - * incoming AArch64 regs received from 64-bit KVM. - * We must perform this after all of the registers have been acquired = from - * the kernel. - */ - if (!is_a64(env)) { - aarch64_sync_64_to_32(env); - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); - if (ret) { - return ret; - } - - /* Fetch the SPSR registers - * - * KVM SPSRs 0-4 map to QEMU banks 1-5 - */ - for (i =3D 0; i < KVM_NR_SPSR; i++) { - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - el =3D arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i =3D bank_number(env->uncached_cpsr & CPSR_M); - env->spsr =3D env->banked_spsr[i]; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arch_get_sve(cs); - } else { - ret =3D kvm_arch_get_fpsimd(cs); - } - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpsr(env, fpr); - - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpcr(env, fpr); - - ret =3D kvm_get_vcpu_events(cpu); - if (ret) { - return ret; - } - - if (!write_kvmstate_to_list(cpu)) { - return -EINVAL; - } - /* Note that it's OK to have registers which aren't in CPUState, - * so we can ignore a failure return here. - */ - write_list_to_cpustate(cpu); - - kvm_arm_sync_mpstate_to_qemu(cpu); - - /* TODO: other registers */ - return ret; -} - -void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) -{ - ram_addr_t ram_addr; - hwaddr paddr; - - assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); - - if (acpi_ghes_present() && addr) { - ram_addr =3D qemu_ram_addr_from_host(addr); - if (ram_addr !=3D RAM_ADDR_INVALID && - kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { - kvm_hwpoison_page_add(ram_addr); - /* - * If this is a BUS_MCEERR_AR, we know we have been called - * synchronously from the vCPU thread, so we can easily - * synchronize the state and inject an error. - * - * TODO: we currently don't tell the guest at all about - * BUS_MCEERR_AO. In that case we might either be being - * called synchronously from the vCPU thread, or a bit - * later from the main thread, so doing the injection of - * the error would be more complicated. - */ - if (code =3D=3D BUS_MCEERR_AR) { - kvm_cpu_synchronize_state(c); - if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr))= { - kvm_inject_arm_sea(c); - } else { - error_report("failed to record the error"); - abort(); - } - } - return; - } - if (code =3D=3D BUS_MCEERR_AO) { - error_report("Hardware memory error at addr %p for memory used= by " - "QEMU itself instead of guest system!", addr); - } - } - - if (code =3D=3D BUS_MCEERR_AR) { - error_report("Hardware memory error!"); - exit(1); - } -} - -/* C6.6.29 BRK instruction */ -static const uint32_t brk_insn =3D 0xd4200000; - -int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) -{ - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; -} - -int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) -{ - static uint32_t brk; - - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk !=3D brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { - return -EINVAL; - } - return 0; -} diff --git a/target/arm/meson.build b/target/arm/meson.build index 5d04a8e94f..d6c3902e67 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -8,7 +8,7 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'k= vm64.c'), if_false: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), i= f_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714816; cv=none; d=zohomail.com; s=zohoarc; b=TnVJqtRMocbXvSAIp4GTCze/MPYrgpBQ+94ffNlGe0SDXT45v69GkCcOp1TJofApsSV26a+A4bovP0mm2BVi2GuuHE/u1EUjBhQnVfreLNBqnSIaKuLkKnrT+dCycBZyWHQc40wR3SF5eWv1H83TNwuXtFoRzqCGuOKBPAk3/qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714816; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=z9sYIWas5f3L9LVklxkBAZhldZmGtqlfaE/Pn9tmcPw=; b=RByukb9Lv7NeQqaQqvAQkyPBTusdYs5fUDfoETyS2bsXtbOKEjirccKX1vyDcWgB6vAlUfPNL4VulTgk+0LARvT80RpNRQzm7hNcaTRJsheZG4aDQ9vNSwHgxHpetnyOxzVmxCMWAt53J6Bzx6KHg3qYx+p0LeO78p48+m54SK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714816966417.661584799322; Wed, 22 Nov 2023 20:46:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YK-0006br-T8; Wed, 22 Nov 2023 23:43:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y5-0006QL-Mg for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:46 -0500 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Y0-0006EW-Kl for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:45 -0500 Received: by mail-ot1-x330.google.com with SMTP id 46e09a7af769-6d7f665285aso267195a34.1 for ; Wed, 22 Nov 2023 20:42:38 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714818183100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 12 ------------ target/arm/kvm.c | 12 +++++++++++- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1043123cc7..b96ff35e34 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,18 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_vcpu_init: - * @cs: CPUState - * - * Initialize (or reinitialize) the VCPU by invoking the - * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature - * bitmask specified in the CPUState. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_init(CPUState *cs); - /** * kvm_arm_vcpu_finalize: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 466b848156..a864d0852f 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -58,7 +58,17 @@ typedef struct ARMHostCPUFeatures { =20 static ARMHostCPUFeatures arm_host_cpu_features; =20 -int kvm_arm_vcpu_init(CPUState *cs) +/** + * kvm_arm_vcpu_init: + * @cs: CPUState + * + * Initialize (or reinitialize) the VCPU by invoking the + * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature + * bitmask specified in the CPUState. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_init(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); struct kvm_vcpu_init init; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714558; x=1701319358; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XoNhjamHa23uC1hFwLD47ZBDARlMJkpmLpzYJFJqrbI=; b=ei+ILln1SJpymayDqmD50fVEU7Yxr+21oTx6JFJB3DWSnHd09em8ejKrpzuuC7brX3 dIrRrENXCshKDeGx+W6V8z+Owf44aiKGj70ip/XZH43COduCV/J41T5L1lh0k76bLSIL b3qoJ9CehkOJFJoPHoIo+AqtNuW+M0xfP0PiiCmZQXi7Tbfo+LI/KFb4jJnYe5qt+vNo 3HZLh45WKFQWykKkl8aRGzDbjkvKMl3/OTgZzLZSos+4nzzgS8unZ2085b6fxSLBOt8i p1hJzu/8ApWxkmyUwYofoerp+sRvFf5hOyEojDFv4cyrW4I9DDT/xvqElxs15wAigRal aOEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714558; x=1701319358; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XoNhjamHa23uC1hFwLD47ZBDARlMJkpmLpzYJFJqrbI=; b=clYWrZPXu8OeVN16hJkRgBBsi4vdrnZ1kJmt3VEP61fjWV9RBFiHAAhP2wpNzDa6iC 3BTu8pNM+aqPHpsl3emnsGRXtN7w+n+VkOiJLUmO3rKb5WC6fQNio7Zq/FHLW4FoCguh cPIQQPp0O4MqazLar7t0q/nVK2+qSEQ3z5svrrBRotqi9Grby2udzl8dYQBHL+W95e4r MyCDlWfXw/xninJZYddKRZhqH4aMlnJ6vcyhd0MRWS31xl19KWc7vnQmJudDXaoKcjqk /jfVNInP9T+3G21k9LC0vSzM8wX03Ev+gpylNH7qWDm/+0U8SUespV7gRtoZrbf2OlYj klqQ== X-Gm-Message-State: AOJu0YzyPZEBLEUZDEdG/kLq/mAhuOs/vFjsbFLkcNbxn8fR/Ap+uyHe kPt6OPRn0LICnuTDMfGjnvwdzOSFrFrmhl0J2Xj4bJpr X-Google-Smtp-Source: AGHT+IEpW+HZ6DapZSL5u9uJzBb66/sGjP2TPOmY656i5Sr/kyDRuPVwM7NEpOrd+dMS38aOj2urYQ== X-Received: by 2002:a05:6870:1f1a:b0:1f9:52e2:a8d7 with SMTP id pd26-20020a0568701f1a00b001f952e2a8d7mr4751694oab.43.1700714557955; Wed, 22 Nov 2023 20:42:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 16/21] target/arm/kvm: Unexport kvm_arm_vcpu_finalize Date: Wed, 22 Nov 2023 22:42:14 -0600 Message-Id: <20231123044219.896776-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714944823100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 14 -------------- target/arm/kvm.c | 14 +++++++++++++- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b96ff35e34..9b630a1631 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,20 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_vcpu_finalize: - * @cs: CPUState - * @feature: feature to finalize - * - * Finalizes the configuration of the specified VCPU feature by - * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring - * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of - * KVM's API documentation. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_finalize(CPUState *cs, int feature); - /** * kvm_arm_register_device: * @mr: memory region for this device diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a864d0852f..20d8c81667 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -79,7 +79,19 @@ static int kvm_arm_vcpu_init(CPUState *cs) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); } =20 -int kvm_arm_vcpu_finalize(CPUState *cs, int feature) +/** + * kvm_arm_vcpu_finalize: + * @cs: CPUState + * @feature: feature to finalize + * + * Finalizes the configuration of the specified VCPU feature by + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of + * KVM's API documentation. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) { return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714949; cv=none; d=zohomail.com; s=zohoarc; b=jApw+9H5rj41K82AgUFF+0xeuhJMdF4LOVIWiBn4oX5E60oNjXNWZic0ghNxL2nWsAd02MpMu3IXamF2KOrkGDL5BzMTuvHSQpBr9/zZGQZ15aU26XbQeCFXLf7MXCCtTe8qi+P8cWySdmk6ee61c0Anm/9aNa4gL3cENZOwdKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714949; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VkzgPDpougz5Puiw+xECKRO2grc7zzyhXDofA8x6EVo=; b=KL9zG8TYZTG2RLJFUFEcNy5huOlzNOnMUqj+RvIpV9SAgk1P0z5XKDFlQ8dQgNz9NYoe7WWgnPi0F/7mpkIZ7dQt+x9l12LRDKimVMH45OE7A8JyvWbSroRd93wu4hv7pFZVdLuCSNmfWaoVmVJaHiLSPMfakVlmLXdtVrjGDls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714949458548.8136003715096; Wed, 22 Nov 2023 20:49:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YL-0006d0-NM; Wed, 22 Nov 2023 23:43:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y6-0006Rs-Qp for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:48 -0500 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Y2-0006FU-A0 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:45 -0500 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3b5714439b3so283742b6e.3 for ; Wed, 22 Nov 2023 20:42:40 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714950755100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 12 ------------ target/arm/kvm.c | 10 ++++++++-- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9b630a1631..350ba6cb96 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -39,18 +39,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t gr= oup, uint64_t attr, int dev_fd, uint64_t addr_orma= sk); =20 -/** - * kvm_arm_init_cpreg_list: - * @cpu: ARMCPU - * - * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). - * - * Returns: 0 if success, else < 0 error code - */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 20d8c81667..bc4ba7628b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -789,11 +789,17 @@ static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t= regidx) } } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's +/** + * kvm_arm_init_cpreg_list: + * @cpu: ARMCPU + * + * Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). + * + * Returns: 0 if success, else < 0 error code */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu) +static int kvm_arm_init_cpreg_list(ARMCPU *cpu) { struct kvm_reg_list rl; struct kvm_reg_list *rlp; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714696; cv=none; d=zohomail.com; s=zohoarc; b=hlJBSCUz7z/ZYW3HB+KdvwdJ8BzmSx1tRbJFWqUCW48hd1RvIKQSJXuMEA7p5Ts7TJrEhWDB3IwH0HfkJrV+3fs34NIrdTenMlNQmyweFb+NL9c/7UEuok+gQkMr4qfltVStj+vQxtWPYK6rG9HuLnDIy1Nqhw/YOJmzMFQmHBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714696; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2iSZMQtowpDEmNjGPUjOpszRYxZbjV35t/gkG9vRYI4=; b=nBPRpXFTPc5KcngI5IkLwaLDgcRzxnBuqdSNgAIRjTzk+ekTrDGtlyaaKGcqO36so6ycoYsd8DBc2oi0gNMwC7QMIyIPHY5CulAo71XBdWAV73zRNtGzFWYAldNJaR25fhvDVLwfJoOhuiEcd1eLEUVuuoaXSqjAy84GuNKgwJI= ARC-Authentication-Results: i=1; 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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714560; x=1701319360; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2iSZMQtowpDEmNjGPUjOpszRYxZbjV35t/gkG9vRYI4=; b=W9L/RIqoAQBzuw3sum3jbM5n8l3KwBU/9ZPt4lG/XoKM9rBq6Yz+832Fo/6dqhIcoN xK1WHQkafAMXV79EFuoW18iY+nGhSeZPTGZvG2YPfisIl6WKmf6yWs0L6ATSwKo3CXDH QLGQxoC00Wq2xjFrNTqpQ/Q7ivAMJmAuhSxl0Iv7WdMThomPT1BpaXoOuyyU6nQEm5QK 1jlez+wjoU4mVZa3z0fNQIok0Mz6MHpHEPzTHKom10ZH2+YBeRfiDfObja2qHWY3Fh85 OUGL4hl4zKhttK0MOjCOsGidqHqlTlBarb2oLQW8DR8Xz/f7E+/Z4VgYRvk5uFDlHY3R zvGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714560; x=1701319360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2iSZMQtowpDEmNjGPUjOpszRYxZbjV35t/gkG9vRYI4=; b=JqLX46p+h5UVmlaoIJemBqbCy5MBmLXQt5qlaX3kLZdUvNNCiizZHOBeD59Fb/d3Go Js6HUTguZiJHmnK5gNqppYUlOFdh0szQu5AsvSN3SpfI+MI7lHx7lb/pdIKSK2wr6Fyx 1nDAxrTNtfFHrxq9V8hGQx+os0S122R7jrnRb9R8oZrV32ks8lVFwhmd+sgA1wfc6VBu LLbkUPZRDWMIdxALcC1Oh/7gwLbqhQD3tTgWZzZCGBL1t0yyjrw8kC7hbRIlbDoD7913 CkSnFtdrLfWPp/PKk0CW4CviExsEcZTgAIqhLDIvFKZoJj4CreCRsPDZUzxk9iKvEiTk jyQQ== X-Gm-Message-State: AOJu0Yz/Q5iSCmfrz6dCClKJjR9QOs35J+qJlfAs58m/4OA8YIL3u1zi wwWdb14YjHu6ar1RdqFpTwsSckVODozWxkdOFe8jf/lT X-Google-Smtp-Source: AGHT+IHM5SR7BfMp+++fBemOjmQneHyqpOOD1guFoMrhjSfeB15iaQFqVmuYdOzratxzDyM15JXVmA== X-Received: by 2002:a05:6808:1247:b0:3b2:dd32:2fe9 with SMTP id o7-20020a056808124700b003b2dd322fe9mr4916802oiv.35.1700714559780; Wed, 22 Nov 2023 20:42:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 18/21] target/arm/kvm: Init cap_has_inject_serror_esr in kvm_arch_init Date: Wed, 22 Nov 2023 22:42:16 -0600 Message-Id: <20231123044219.896776-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714697813100001 Content-Type: text/plain; charset="utf-8" There is no need to do this in kvm_arch_init_vcpu per vcpu. Inline kvm_arm_init_serror_injection rather than keep separate. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 13 ++++--------- 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 350ba6cb96..1ec2476de7 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,14 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); =20 -/** - * kvm_arm_init_serror_injection: - * @cs: CPUState - * - * Check whether KVM can set guest SError syndrome. - */ -void kvm_arm_init_serror_injection(CPUState *cs); - /** * kvm_get_vcpu_events: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bc4ba7628b..3250919273 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -96,12 +96,6 @@ static int kvm_arm_vcpu_finalize(CPUState *cs, int featu= re) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } =20 -void kvm_arm_init_serror_injection(CPUState *cs) -{ - cap_has_inject_serror_esr =3D kvm_check_extension(cs->kvm_state, - KVM_CAP_ARM_INJECT_SERROR_ESR); -} - bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, int *fdarray, struct kvm_vcpu_init *init) @@ -562,6 +556,10 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 cap_has_mp_state =3D kvm_check_extension(s, KVM_CAP_MP_STATE); =20 + /* Check whether user space can specify guest syndrome value */ + cap_has_inject_serror_esr =3D + kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); + if (ms->smp.cpus > 256 && !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { error_report("Using more than 256 vcpus requires a host kernel " @@ -1948,9 +1946,6 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - return kvm_arm_init_cpreg_list(cpu); } =20 --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714891; cv=none; d=zohomail.com; s=zohoarc; b=Z8dX0QMqofX6AuE3BXOqthhKjLgLg0qINrK35Bv31Z6WGId0mYYgfSXoqpB/uow4TSjtKzvy2QyAFbpcXaVfwcBVjE2WvZ3voovKqaQmC+Rx4Q66OqDEt+ZdMibzBNnnEYq7t/smvHEQ6R5otN5OflE4prgUnWaSJVqMlblW+Uw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714891; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wiXhFHZySPL8w40Zgeyi5JXzqLc7WVTgj0ZvaUr0XG8=; b=jdZnG2JSb6tFAu86/qOpZnpC2LfvvGZstYXcGQZCGuL7bUdmYnkBYSPuXLUwTakCbzk+1NZqzyfa3k2a7vDzWrwGV5/w0pQ2sXqMEWSIG5IuMnwnm0CGsXUy5C/gsYKMYPpNXTnpSgeRxI7UX3mDMIc9+gFi1ytRyb6kqFaJS7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714891584924.8388498521774; Wed, 22 Nov 2023 20:48:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YL-0006cq-N1; Wed, 22 Nov 2023 23:43:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y7-0006SZ-1M for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:48 -0500 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Y4-0006Hf-0n for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:46 -0500 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1f93d0cd2ddso333322fac.1 for ; Wed, 22 Nov 2023 20:42:42 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714892466100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 20 ++++++++++++++++++-- 2 files changed, 18 insertions(+), 22 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1ec2476de7..b4339d49d1 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,26 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); =20 -/** - * kvm_get_vcpu_events: - * @cpu: ARMCPU - * - * Get VCPU related state from kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_get_vcpu_events(ARMCPU *cpu); - -/** - * kvm_put_vcpu_events: - * @cpu: ARMCPU - * - * Put VCPU related state to kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_put_vcpu_events(ARMCPU *cpu); - #ifdef CONFIG_KVM /** * kvm_arm_create_scratch_host_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3250919273..f9aa55b1a0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1092,7 +1092,15 @@ static void kvm_arm_put_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty =3D false; } =20 -int kvm_put_vcpu_events(ARMCPU *cpu) +/** + * kvm_put_vcpu_events: + * @cpu: ARMCPU + * + * Put VCPU related state to kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; struct kvm_vcpu_events events; @@ -1121,7 +1129,15 @@ int kvm_put_vcpu_events(ARMCPU *cpu) return ret; } =20 -int kvm_get_vcpu_events(ARMCPU *cpu) +/** + * kvm_get_vcpu_events: + * @cpu: ARMCPU + * + * Get VCPU related state from kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_get_vcpu_events(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; struct kvm_vcpu_events events; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714807840545.8839255110655; Wed, 22 Nov 2023 20:46:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YM-0006dW-Eo; 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([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714562; x=1701319362; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QMxrWeuiHOLByxeE5N6Cs/cc7NkJUHDeIn2aLelpULE=; b=QGdVhUsKc5Ko4aCEd/QuwPa5MF68JTZuE3ZVVI/vAz0zeyHTqtlikRzHX1eg+dEe5I AvBrV2MQ5u4kYAgSeHXd2IxEwoBc3hLQCHzwQFC8DshpDE7ajNssMTaPznqOI2VHaAZH UuEOjz++0fit43Xi7bzZm3/HbNtiPpXkburwtPVaBD4P5jliIGuLB9elpOTU+ShcQzFQ WRJlwtg2vqRmrdBW/Nf0D28P5s4de6tgU4cU+ATlgnwaaOHjNwvUKqcOM31WZ9nN3ZTc N5MvX7I8ID0Jfo1v9qUTMQtNRg2JcFmVQr8b88+Y9vvGoMnJVc15RVMAt1+eHR8rJTdD NEBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714562; x=1701319362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QMxrWeuiHOLByxeE5N6Cs/cc7NkJUHDeIn2aLelpULE=; b=OXe6t3oEIDfQW8n2sL3/uMQ+AuvI7ogFEz+wlm9UHtOE6niJ/kBIsAEIggr2rIk/s5 p7DhtlP3F6fNOblGCrgc/D/Okt3ky5frL5Q35hEV8HJkyzRw4P/srEr2/U4r5Dz6Ot4/ /fc5m7MLBtiqM2MUAH+w1vPCFX24UwaGSLxcsp5fJgqBPbxtwTEW04mLsAYlUKoI6RhW 0ffINa6XQBRsWTQxWtlwYHIilbAXF/eO7p4OrcCOo8oTxfUD/0BbN2vNo+g1m1tdYdws Fxr+PiuJ2sgZZVILarKDGcOWVR8UssLSS2g14KQ32x98Ufk924NTruEfn6V4PfsvSGrm 1L4A== X-Gm-Message-State: AOJu0Yxi6okzhhPIB1Fvc21Zd/26hWTBu87loEHY3LdTxCDMcPPdODwW tIyrWFZ4GfIl/S8x4zG01/NS0MagEl9fEKYtBfExy9aO X-Google-Smtp-Source: AGHT+IHJsOa7qNEOJzfrry7beIAknR39vUMO6yPd+pVe1flEUkVOj5KQe1c3dTwCFGZSQLuFo36x9A== X-Received: by 2002:a05:6808:1a0d:b0:3b2:dfa0:aea3 with SMTP id bk13-20020a0568081a0d00b003b2dfa0aea3mr5571900oib.3.1700714562036; Wed, 22 Nov 2023 20:42:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 20/21] target/arm/kvm: Unexport and tidy kvm_arm_sync_mpstate_to_{kvm, qemu} Date: Wed, 22 Nov 2023 22:42:18 -0600 Message-Id: <20231123044219.896776-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1700714808138100001 Content-Type: text/plain; charset="utf-8" Drop fprintfs and actually use the return values in the callers. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 23 ++++++----------------- 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b4339d49d1..8a44a6b762 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,26 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); =20 -/** - * kvm_arm_sync_mpstate_to_kvm: - * @cpu: ARMCPU - * - * If supported set the KVM MP_STATE based on QEMU's model. - * - * Returns 0 on success and -1 on failure. - */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); - -/** - * kvm_arm_sync_mpstate_to_qemu: - * @cpu: ARMCPU - * - * If supported get the MP_STATE from KVM and store in QEMU's model. - * - * Returns 0 on success and aborts on failure. - */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); =20 int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f9aa55b1a0..19454f432a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1006,41 +1006,32 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) /* * Update KVM's MP_STATE based on what QEMU thinks it is */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state =3D { .mp_state =3D (cpu->power_state =3D=3D PSCI_OFF) ? KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE }; - int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); - if (ret) { - fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - return -1; - } + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); } - return 0; } =20 /* * Sync the KVM MP_STATE into QEMU */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state; int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); if (ret) { - fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - abort(); + return ret; } cpu->power_state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPE= D) ? PSCI_OFF : PSCI_ON; } - return 0; } =20 @@ -2184,9 +2175,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; + return kvm_arm_sync_mpstate_to_kvm(cpu); } =20 static int kvm_arch_get_fpsimd(CPUState *cs) @@ -2367,7 +2356,7 @@ int kvm_arch_get_registers(CPUState *cs) */ write_list_to_cpustate(cpu); =20 - kvm_arm_sync_mpstate_to_qemu(cpu); + ret =3D kvm_arm_sync_mpstate_to_qemu(cpu); =20 /* TODO: other registers */ return ret; --=20 2.34.1 From nobody Wed Nov 27 04:43:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700714698; cv=none; d=zohomail.com; s=zohoarc; b=kIGMlwVLADuCdcR8+qhFToNcD83f226LZLzR2+DyRkoMq1mupoOQu4WND+GuR6E5cq/rbuj/ckGM1mGiWXQ0XGrp6aBT6asY3394MwQf4uWUGVzkIrAPdvjOJ3HoQ6djH9/Xob1SlKnEagss6ZEVGn7VJdPyQ29/HNcicM9ZvJI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700714698; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TngP5H8NgKVtRrs3cV2eef3xZ01hrk4ilINuJfIwbMU=; b=lh69hGoFrU2gh7vG8kzvNBjubRx5gTCOqGLv/QVID954m/LJXk7HFqW79JisIIVbR1sEp/lw8vUeylqAFtD5U/IEDHlGguOJhAqf6fN6vJCuBfOEFcNK6pOD+Cl04TEQfIB4WtBgSObJ1uPAtaAFy2tajsUtk68iDBosJ1pGGvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700714698274677.723287963331; Wed, 22 Nov 2023 20:44:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r61YX-0006gX-MD; Wed, 22 Nov 2023 23:43:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r61Y7-0006TK-Gc for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:48 -0500 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r61Y4-0006I2-9N for qemu-devel@nongnu.org; Wed, 22 Nov 2023 23:42:47 -0500 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3b2e4107f47so359406b6e.2 for ; Wed, 22 Nov 2023 20:42:43 -0800 (PST) Received: from stoup.. ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id i7-20020a056808030700b003b8347de3c2sm73888oie.19.2023.11.22.20.42.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 20:42:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700714563; x=1701319363; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TngP5H8NgKVtRrs3cV2eef3xZ01hrk4ilINuJfIwbMU=; b=pKJ/O4nj9LiM72l+6N3miXDNQABKIEsXBipI0o1p4cNOAgYqV9x3ZeBkSKMzHjqk9g RdP+V5jqEcRdReLbFphRMK2/grvhpi41gPvK22FtNA2lilylpnVmt7BcddpkzAwR2bl5 vDZM0JtnQ3uqOdSCzDbTbAXDbzq2Erko3GMCxy2/Hgf2eHbfDxNQCRUI+v30F99vLOby e5+vMVJbzeSGxXb2Oi/QlYq2CC8ppEO8xIgUcTFKYEP8PjiAK3WYLo9ZJgHgksZaAk+C v4NQchOOsaKGjMHEDNW3e7BYOmllssA1v5crKsMxSO/EVuZmQgsXd4AXuM1vNikQ+15e 6bNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700714563; x=1701319363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TngP5H8NgKVtRrs3cV2eef3xZ01hrk4ilINuJfIwbMU=; b=v1ilp1juRCLCboUNIpZxMGBnU/s3U9NvoMVr6NXAXY6n4hCX8I6YJWMHqe7zHyMqgR KWwjdEJoZdrcqYP2uACuA/dn6YBH+OGTXpO8Og5kID8v6OKQ7Akxod793zRbmP4ss5kb Q7XWr49ElQuGVQHbxvtVARP2XPJp6Ge7aS9TZI0AQhxwfjmRnJ8+1R/wSb5/+Z4jIity KTbHFX2KPN/t6kpGRp9wTCADER/sl9VD+iobGk+4N6zkTmQaF2hS3I41lDdCqkTEpDWv wL+o5sjZYhywTaeGPZptCUmU2SZE/JPH69CUnP8/mSJ3sjXt9ghoSWX+vAOYiUdlqGqV 3efQ== X-Gm-Message-State: AOJu0YyCV6JFJEvcTLNr9xKlYIys6axRmi8zxzh38faGibPYYqsjgQe+ BWzPSdi6AiekkxbSr+zTuFg6W5Wt6wsTlfM8/bhx+9rD X-Google-Smtp-Source: AGHT+IFtj7S4KU+XONJgdhB67AuP4TwL93ur3uJiBiQLEyELOZuOT9dUy/9bmPcxLFfDaYCDo1cWMA== X-Received: by 2002:a05:6808:5c4:b0:3b0:daf8:954 with SMTP id d4-20020a05680805c400b003b0daf80954mr4578312oij.49.1700714562882; Wed, 22 Nov 2023 20:42:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 21/21] target/arm/kvm: Unexport kvm_arm_vm_state_change Date: Wed, 22 Nov 2023 22:42:19 -0600 Message-Id: <20231123044219.896776-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231123044219.896776-1-richard.henderson@linaro.org> References: <20231123044219.896776-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700714699809100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 2 -- target/arm/kvm.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8a44a6b762..2037b2d7ea 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,8 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); =20 -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); - int kvm_arm_vgic_probe(void); =20 void kvm_arm_pmu_set_irq(CPUState *cs, int irq); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 19454f432a..6e3fea1879 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1290,7 +1290,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm= _run *run) return MEMTXATTRS_UNSPECIFIED; } =20 -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) +static void kvm_arm_vm_state_change(void *opaque, bool running, RunState s= tate) { CPUState *cs =3D opaque; ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.34.1