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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id f3-20020a05600c43c300b003fc0505be19sm176312wmn.37.2023.11.22.10.31.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700677862; x=1701282662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E7103XOFxT5bJSMqrbJRnaAZtCqt8Oh3G3I/DOAsQEM=; b=XudJ9G9i3I3FSZCHQA6DVEod88neTJm5dbjN+lB3MnansF4zmSW7DdweYcwUnYHypc CoOvqM4jd4EjaxKeFhhCW2GRHB2/aWQFTntHwKCEwKOPUOsnMVLoL134zJmjHsAq4oFL Dw1P3hTnZuqvUIabYn0Jhzwk6evKhY0l5hx5Oy2RLQoA/UczR9cqoUb3i3ksNrxJYHSY ZnBnwXQaTz3oRPSvccFbKDKuqjUe5yNAfTrxSAuV1b6RZvFwMjFXgn5vk9vAr+qFCFuc NwV4mnj/JZYYcwU7XUaKRxLqi/zxu3NnGO7RAIly0tWd1xabcfv7HjPMIQhsXWhnSNOZ VT7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700677862; x=1701282662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E7103XOFxT5bJSMqrbJRnaAZtCqt8Oh3G3I/DOAsQEM=; b=Qvho+TOsW60c+ZNOyGp1O8bnO0xpBCc5n7ZtTPM7kWCBHxth+0pORJ2TEbgs+tk0RW DAfVfNDOzZrcyz35AjHibF+SkhxbOjuQnMtOGp39RjJLb0UcfcjktpGCZiven8KhKMzd yWVNw0wGzF5PPRZry8zqob5fEuNQwyqEGfO3s127qzI47H/czAiUE7bHrfGZPeXu49kI M6RptCdihz3QzxAJaMEcVYaP4jy4ButFOAWiTKsk0iR6j2TRLOdEHUNscY9A4i7q9TMv +NoG+VfiZy4AlGY72x7EXf4FmKvYgzXu+/Mr53SWAmVp9Vj9rt2Z6PMZEGBwIMTzcE5h /J4g== X-Gm-Message-State: AOJu0YzQ32cTLDoYFM2Pc/3bPXK2pOX7H1VYwP4ANGeGjQhoTAkWnYDp ZZsOuoSn5oJVddhBuYbgGIaMm3V7+zVBGUM3sJM= X-Google-Smtp-Source: AGHT+IHIV10IErfFC07Es1yMjpQsHxoU13Fz1+eiamPARf56zp7ZGthltp+wH8DZLOe8g00EO/RHvQ== X-Received: by 2002:a05:651c:21a:b0:2c8:7c22:97e2 with SMTP id y26-20020a05651c021a00b002c87c2297e2mr2064877ljn.45.1700677861838; Wed, 22 Nov 2023 10:31:01 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 02/11] target/arm: Add target_aarch64_available() helper Date: Wed, 22 Nov 2023 19:30:38 +0100 Message-ID: <20231122183048.17150-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700677985748100003 We want to build HW models once, but don't want to register types when all prerequisites are satisfied. Add the target_aarch64_available() to know at runtime whether TARGET_AARCH64 is built-in. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 02b914c876..bf6b3604ed 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,4 +33,6 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) =20 +bool target_aarch64_available(void); + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 25e9d2ae7b..1990c04089 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2548,3 +2548,12 @@ static void arm_cpu_register_types(void) } =20 type_init(arm_cpu_register_types) + +bool target_aarch64_available(void) +{ +#ifdef TARGET_AARCH64 + return true; +#else + return false; +#endif +} --=20 2.41.0