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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id d11-20020adfa40b000000b003232380ffd7sm38237wra.102.2023.11.22.10.31.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700677909; x=1701282709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G9IPEOr0rBXMMdMMcbayFM6zic8FKV6LVlnxUz4MJGo=; b=CGUlveBtcf6sVTbFmIFKpNOwPRCdwQZZTtImAOLUjN+DmSgYiGK9xrcXqvj76DAo19 rssEi+4Vws9ooltW/C3MDJybOKHFI43eqaBP7v4M/FMBPWwAsiFHtzmPrJHx46ZsPnk4 PUzXgN5YA2Lfpk16t3/dzq3bukWP+YejbjKKnn/HBByhRyqYse96NnKiEL+BtE85/XcH WtFWQBK0gl2a9ctJv6BTTYqr/mUGkwSZQESq6bqakKDxXTVl6eIJzp11/YZVPr8fXj/x 4Rj9DYbds5+pkphSoKRZeS/xhGdtyoRlnsYoI99Z8wZaJHiOrymldIPD0LdVjXDP8tHK 6H9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700677909; x=1701282709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G9IPEOr0rBXMMdMMcbayFM6zic8FKV6LVlnxUz4MJGo=; b=bHwYwc+T6TOTvlYqCYd4YrMvOemLnUAQhGn40nKV9VuexXccUi7uryvBztUAgdJ5Cv OJLQZYrmBfvOihCeHjOoX0MXHSTC3nPTrvb2gDya+JBuhyhXiNW4wE1lZpzGn6Zl3ff7 Pf1OK6fvpLpaLJ5RqnKSVylbcHo5F9v12gb+NkRdWErUrMDDhUvuL75ISZ8ZPyuGf4Rg V6dNcQC+uuipuUNQ+U/wsSbCgbrbdNxo+AXxbd5Wudu8fhXZvROewbnAuKny4gJ3Ht+G mIPVNBgKpiQ4yRDgGeB6Z1OmQM6VL2VBmlHxkvCTST+oJcjaMoZOffCILgNFB7+vZXxC al4w== X-Gm-Message-State: AOJu0YwCUVdQnxAlYQFi/uvsbDHfaq5X9NIz/CpfzFUg545HTZtIfV2n WiFOtRRhogeGi1GUrw8awK0+QPm4YffjzYbCJ20= X-Google-Smtp-Source: AGHT+IH5oUX5HGY8Tyq5COBq6B13fWkNiw9fUgbBMXCor3h0U1nUKnPUvYvsxmr+d4l3j0e+BaAyXw== X-Received: by 2002:a5d:6c6d:0:b0:332:ca1a:a824 with SMTP id r13-20020a5d6c6d000000b00332ca1aa824mr3142903wrz.11.1700677909262; Wed, 22 Nov 2023 10:31:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 11/11] hw/intc/meson: Simplify how arm_gicv3_kvm.o objects are built Date: Wed, 22 Nov 2023 19:30:47 +0100 Message-ID: <20231122183048.17150-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700678035962100002 Use the target_aarch64_available() to build the ARM_GIC_KVM types regardless the ARM/AARCH64 targets are selected, but restrict its registration to TARGET_AARCH64 presence at runtime. This will help to have a single binary running both ARM/Aarch64. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/arm_gicv3_its_kvm.c | 1 + hw/intc/arm_gicv3_kvm.c | 1 + hw/intc/meson.build | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index f7df602cff..b3063c4cd7 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -261,6 +261,7 @@ static const TypeInfo kvm_arm_its_info =3D { .instance_size =3D sizeof(GICv3ITSState), .class_init =3D kvm_arm_its_class_init, .class_size =3D sizeof(KVMARMITSClass), + .can_register =3D target_aarch64_available, }; =20 static void kvm_arm_its_register_types(void) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 77eb37e131..33321dee5d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -909,6 +909,7 @@ static const TypeInfo kvm_arm_gicv3_info =3D { .instance_size =3D sizeof(GICv3State), .class_init =3D kvm_arm_gicv3_class_init, .class_size =3D sizeof(KVMARMGICv3Class), + .can_register =3D target_aarch64_available, }; =20 static void kvm_arm_gicv3_register_types(void) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index ed355941d1..d45eb76f36 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -40,8 +40,10 @@ endif specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common= .c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_co= mmon.c')) specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cp= uif.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) -specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files( + 'arm_gic_kvm.c', + 'arm_gicv3_kvm.c', + 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) --=20 2.41.0