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[176.184.5.64]) by smtp.gmail.com with ESMTPSA id b5-20020a05600c4e0500b003feae747ff2sm261799wmq.35.2023.11.22.10.31.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 22 Nov 2023 10:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700677898; x=1701282698; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=juSImIqOFX4cBg5Zc+Do2T+lJUxoOW0iOapk4mN+Z7o=; b=HYm4Qm6T8RPZspq0QC/9ILxuDUOlrpei8Dlmyju6RtFlBex4tXpdag8vXyGKMNihvu 4TX5YpXceDlDSOBQ4babeDEKGr1zLWzfSdi69Ggdsl1RPvr3+iCSqRjVY8Ignh06HqiC miI1k+K5QljjCGSBuPgtjKH+VMAAHNDD9F42wOcuUYpLC+fxlkgV+koQd8DcFhs5wVhx xSmlYR0UFnMrUu0OeT3J76LFareVEbZgPW1/UT23Tq4sxrsvVsp7xUwDGnNt2x8FuoPM uwkLFl54juhBvsILdYmr/BfKcODTPd4/zR+VdKgMpuCidhZwrLch/pClxACCBk5f/58O WLBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700677898; x=1701282698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=juSImIqOFX4cBg5Zc+Do2T+lJUxoOW0iOapk4mN+Z7o=; b=KLWw8n+tGDxXRn/u4M/NlFrE7qLCVTKhRpBiULkSwCmiEInDH287WE+KrTHcjkEeRA xXiO+vPwnlno8afTGF+Kab3Fk79ML7KhszDbwY2DprCuHQD+DZOJdqGtZ9tmHsDtBEeG DBmfFDD/s4I6wnBsJpgl4vpf915TL6aJk2tUR18ZCRQsJmOz7a0ewgpOuOXhRHc85UxT thUpfcvGGaXaAmGFbJ3iawObTRFd7Tojft9+JAD7dFf92LpNMr5vaIpKEZhZc9YbMb+9 g4lLylQAbbFVMLFym3JPWLu3ciFJx7L4IJfgIapSj4P51Jms2BfyX2mURIpQeKhVeQh3 mPcg== X-Gm-Message-State: AOJu0YyLpM8OpcN/JPLaLjfvnBri7QrukWK/F787fwejkblLsD+HavsS FO5agWG9tw8NC6J46PLj2FGVgK2bTLzbSz62C6s= X-Google-Smtp-Source: AGHT+IEDhZssPByOJSwxEJVD+BQeS0gJKpv55Tt6F3/9rP1iAZJ3KJSnJODJSNYMYHo+HTAjjtT9mw== X-Received: by 2002:a05:600c:4f01:b0:409:773:cf62 with SMTP id l1-20020a05600c4f0100b004090773cf62mr2223036wmq.39.1700677898695; Wed, 22 Nov 2023 10:31:38 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Peter Maydell , Thomas Huth , Mark Cave-Ayland , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH-for-9.0 09/11] hw/arm/bcm2836: Allocate ARM CPU state with object_new() Date: Wed, 22 Nov 2023 19:30:45 +0100 Message-ID: <20231122183048.17150-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231122183048.17150-1-philmd@linaro.org> References: <20231122183048.17150-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700678013866100003 The ARMCPU type is forward declared as a pointer to all hw/ files. Its declaration is restricted to target/arm/ files. By using a pointer in BCM283XState instead of embedding the whole CPU state, we don't need to include "cpu.h" which is target-specific. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/arm/bcm2836.h | 4 ++-- hw/arm/bcm2836.c | 19 ++++++++++--------- hw/arm/raspi.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3..784bab0aad 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -14,7 +14,7 @@ =20 #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #include "qom/object.h" =20 #define TYPE_BCM283X "bcm283x" @@ -38,7 +38,7 @@ struct BCM283XState { uint32_t enabled_cpus; =20 struct { - ARMCPU core; + ARMCPU *core; } cpu[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 8031a74600..4f5acee77e 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -39,8 +39,9 @@ static void bcm2836_init(Object *obj) int n; =20 for (n =3D 0; n < bc->core_count; n++) { - object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, - bc->cpu_type); + s->cpu[n].core =3D ARM_CPU(object_new(bc->cpu_type)); + object_property_add_child(obj, "cpu[*]", OBJECT(s->cpu[n].core)); + qdev_realize_and_unref(DEVICE(s->cpu[n].core), NULL, &error_abort); } if (bc->core_count > 1) { qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_prope= rty); @@ -139,24 +140,24 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-o= ff", n >=3D s->enabled_cpus, &error_abort); =20 - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(DEVICE(s->cpu[n].core), NULL, errp)) { return; } =20 /* Connect irq/fiq outputs from the interrupt controller. */ qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_IRQ)); qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(s->cpu[n].core), ARM_CPU_FIQ)); =20 /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_PHYS, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n= )); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_VIRT, qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_HYP, qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)= ); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, + qdev_connect_gpio_out(DEVICE(s->cpu[n].core), GTIMER_SEC, qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)= ); } } diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index cc4c4ec9bf..01c391b90a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -252,7 +252,7 @@ static void setup_boot(MachineState *machine, RaspiProc= essorId processor_id, s->binfo.firmware_loaded =3D true; } =20 - arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); + arm_load_kernel(s->soc.cpu[0].core, machine, &s->binfo); } =20 static void raspi_machine_init(MachineState *machine) --=20 2.41.0