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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d10-20020a5d644a000000b003316db2d48dsm12911463wrw.34.2023.11.21.06.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 06:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700577966; x=1701182766; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=Z/Q0Ze2x0fQAFBtYAYpPfU903dcHJSY8SIbcnM+aFf8=; b=IybLorbYvvGgpeOErkXwOJ4pit3j75PI03VFLK5oMxfehRRMtPARpTqPDPeek0Pt0m tZIcgFYGVpFM3Sq8X39/9B/Gz0usnWXUxXv6Wz4N0Ifxsh5H00PoBsxsZs2uJ1Pk4tqy S5MWPcNOWCpwbRfeC2U9sFhnLLS38mCF8Mg3xsbvqAeKumBwXaq29GVEuUDLjqUbo0kA cv2meTzC+1wLSan9n4EI/SUkivynNYXI+8eUzJlav+dWFLnCgR3i4YY571X4PLUsO2Cc shSML4uCJsI3SVYMbd4wGaDlmkHkNov5SGcNAxLxcTp5Jxhm3HhFIoeme4uPpjgm5fvR EdRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700577966; x=1701182766; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Z/Q0Ze2x0fQAFBtYAYpPfU903dcHJSY8SIbcnM+aFf8=; b=IktRoyubf3pqD63y32kvy0akZn9vUGufH/WY3SfSl/7gja+PcVGgdDQ9BQpVriqjQC UuFuQYOWbT93BzbrqjzmM9o3aJKE9yxU5C1bfCjl8czUiFBUQ4CLbunylYJOX9brniUv 5YUFPL2Vu2N+7do5Dl96BFymVsw6jtRnWa/S/ydV6HQKwlKNtC+qgO+HLYZ5S3aWh22q 6owv46BdHneIWaoQab79wB2C0sYSVCyWcQIkhVdHffdS4EbOuH+mmFAH3wYXSk+hwCho /ZFQF8WDUxPH6Ts1A92/LcWcuyvt07Z+RJDedxympIIa3f8MuLFZ+fKLi4Ni65hxOvfF Oq/A== X-Gm-Message-State: AOJu0Yw0u0McKEFXMXQXmP1K4Z+EYLX6p0MiiF/zUQ2y20Q6v6GtUdH6 wrjuJ4u/EdtxtTc/Zdalb/AMUUL1GPmA2rV9xOA= X-Google-Smtp-Source: AGHT+IEtRsjoJZJyuuN9bOzJcq6GeSc9QAUh5UTj+1Zuji4Iw/Plbl4Cn+yCLEMkuLQrhbcL62+DTw== X-Received: by 2002:a05:6000:43:b0:32f:c3d0:89db with SMTP id k3-20020a056000004300b0032fc3d089dbmr7218859wrx.27.1700577966334; Tue, 21 Nov 2023 06:46:06 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only Date: Tue, 21 Nov 2023 14:46:05 +0000 Message-Id: <20231121144605.3980419-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700578022945100001 Content-Type: text/plain; charset="utf-8" The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I happened to notice this reading through the Arm ARM recently. This is technically a bug, but you'll only notice it if you deliberately look at what should be an unimplemented register to see if it UNDEFs, so I don't think it's worth either putting in 8.2 or backporting to stable. --- target/arm/debug_helper.c | 23 +++++++++++++++-------- target/arm/helper.c | 35 +++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cbfba532f50..83d2619080f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1026,14 +1026,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit @@ -1062,6 +1054,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, }; =20 +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo debug_aa32_el1_reginfo[] =3D { + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, +}; + static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { /* 64 bit access versions of the (dummy) debug registers */ { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, @@ -1207,6 +1211,9 @@ void define_debug_regs(ARMCPU *cpu) assert(ctx_cmps <=3D brps); =20 define_arm_cp_regs(cpu, debug_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, debug_aa32_el1_reginfo); + } =20 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); diff --git a/target/arm/helper.c b/target/arm/helper.c index ff1970981ee..bf26b995171 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5681,20 +5681,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, - { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, - { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, @@ -5729,6 +5715,24 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo v8_aa32_el1_reginfo[] =3D { + { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, + .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, + { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, +}; + static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -8699,6 +8703,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); + } =20 for (i =3D 4; i < 16; i++) { /* --=20 2.34.1