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bh=Uzh7TKgZwwpn2x94O8CB5r9U+Gff10u+dlzoGFMO9hE=; b=D0llMB1eqvVYNnv+ND3LM+qFyr/U553p765WekC8GKXwklDs6+EtW1OZRgoV70wMD+iaPS 3njl2ffUbIycsY9b7SW3j8nl3in+qsfZgzLSB6ioWhVmTXu/f/55dbxaAQZ+3UmYW6j3Re 4g4AtV4T+Dbt9f+eByTMHMSxbpjXloA= X-MC-Unique: o7aA0YwDN7iSrqsailYykQ-1 From: Kevin Wolf To: qemu-block@nongnu.org Cc: kwolf@redhat.com, qemu-devel@nongnu.org Subject: [PULL 9/9] hw/ide/via: implement legacy/native mode switching Date: Tue, 21 Nov 2023 12:53:02 +0100 Message-ID: <20231121115302.52214-10-kwolf@redhat.com> In-Reply-To: <20231121115302.52214-1-kwolf@redhat.com> References: <20231121115302.52214-1-kwolf@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=kwolf@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.035, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700567697470100003 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Allow the VIA IDE controller to switch between both legacy and native modes= by calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_= PROG is updated. This patch moves the initial setting of PCI_CLASS_PROG from via_ide_realize= () to via_ide_reset(), and removes the direct setting of PCI_INTERRUPT_PIN during= PCI bus reset since this is now managed by pci_ide_update_mode(). This ensures = that the device configuration is always consistent with respect to the currently selected mode. Signed-off-by: Mark Cave-Ayland Message-ID: <20231116103355.588580-5-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf --- hw/ide/via.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/hw/ide/via.c b/hw/ide/via.c index 87b134083a..2d3124ebd7 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -28,6 +28,7 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/module.h" +#include "qemu/range.h" #include "sysemu/dma.h" #include "hw/isa/vt82c686.h" #include "hw/ide/pci.h" @@ -128,11 +129,14 @@ static void via_ide_reset(DeviceState *dev) ide_bus_reset(&d->bus[i]); } =20 + pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ + pci_ide_update_mode(d); + pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT= ); pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); =20 - pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); + pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe); =20 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ pci_set_long(pci_conf + 0x40, 0x0a090600); @@ -154,6 +158,36 @@ static void via_ide_reset(DeviceState *dev) pci_set_long(pci_conf + 0xc0, 0x00020001); } =20 +static uint32_t via_ide_cfg_read(PCIDevice *pd, uint32_t addr, int len) +{ + uint32_t val =3D pci_default_read_config(pd, addr, len); + uint8_t mode =3D pd->config[PCI_CLASS_PROG]; + + if ((mode & 0xf) =3D=3D 0xa && ranges_overlap(addr, len, + PCI_BASE_ADDRESS_0, 16)) { + /* BARs always read back zero in legacy mode */ + for (int i =3D addr; i < addr + len; i++) { + if (i >=3D PCI_BASE_ADDRESS_0 && i < PCI_BASE_ADDRESS_0 + 16) { + val &=3D ~(0xffULL << ((i - addr) << 3)); + } + } + } + + return val; +} + +static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr, + uint32_t val, int len) +{ + PCIIDEState *d =3D PCI_IDE(pd); + + pci_default_write_config(pd, addr, val, len); + + if (range_covers_byte(addr, len, PCI_CLASS_PROG)) { + pci_ide_update_mode(d); + } +} + static void via_ide_realize(PCIDevice *dev, Error **errp) { PCIIDEState *d =3D PCI_IDE(dev); @@ -161,7 +195,6 @@ static void via_ide_realize(PCIDevice *dev, Error **err= p) uint8_t *pci_conf =3D dev->config; int i; =20 - pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); dev->wmask[PCI_INTERRUPT_LINE] =3D 0; dev->wmask[PCI_CLASS_PROG] =3D 5; @@ -216,6 +249,8 @@ static void via_ide_class_init(ObjectClass *klass, void= *data) /* Reason: only works as function of VIA southbridge */ dc->user_creatable =3D false; =20 + k->config_read =3D via_ide_cfg_read; + k->config_write =3D via_ide_cfg_write; k->realize =3D via_ide_realize; k->exit =3D via_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_VIA; --=20 2.42.0