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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562287; x=1701167087; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fwjCpEg7CxgIC61BgitQvtOo2gBc/4p1x2tjHLKtQjw=; b=CmYlSFp++lMA0x15vbqc9mWYeKDmgQs+BgJwf+XhTA3g5D3rrCgcAk8SHTbpOxFR7S eYwABQLGyha6vSVLz61kVhYI3faIudkvYLSrISJ95wSB+7AUThgaYQNQs9GAmxB4hg0a qnVxqwZQUg86OMEK2Ggsz81fokRM1k1D85s1oq+YwcefDce9hGjkq2tuJN1KKbSKGjTZ y7lS9xBBDgPhvsrmeRfOd3CNH7epiPAcDimxH3rNiESSUyQDkVtnMUw3NZoPQjDqWMMj S6OIpXZUCv3gi1TNmauZNafM6JCEc3Yz99p5W/avsVfkFBAxhY3TM7VyN+84shzOpCpu MtXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562287; x=1701167087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwjCpEg7CxgIC61BgitQvtOo2gBc/4p1x2tjHLKtQjw=; b=N4HGpXi0CJSUfEGVAscqjQHeSaabglt1M33V5nNIGk75mWfCUyMTvSX/9tipfOrdSt ar2Or2mZS0U1uVZCwgFr9C67gAk52xv6PT74GwwdiAmrhebZLW71hL3TJb4gDKfLk4MX WDVdQbwItSD8ZkAWyhGdsI3yEib4LijeJfLC/tevQFvxKC4y7joN9LwV4ptqmBq9ygR5 jYs0QTlnANkzpOd48NFfY4hW8f3QKX0MloPywyIW+K3gqIDwPccEafSOHFv3JajGc91L q70qP8PlPudbQ9WA0MdaMFYlHUk4+7vDH/FWumjRrduYicMZosZPQKbfTOisDbrZOsPG l3sQ== X-Gm-Message-State: AOJu0YwWctFWvYUqapw0hhwrunaMML7NsvKX6K7SnXmvEaWByQBLijWR psd/4vf++1hd+FlS9SVQLECciAqHILj51FH+fjg= X-Google-Smtp-Source: AGHT+IG8iFFMOe6HPUsEOmnw52AXUg8wZ65gsfaIuH5vtX1PwziiJPlqDvFOj6eHvHe86soLjl042A== X-Received: by 2002:a05:600c:154a:b0:401:bdd7:49ae with SMTP id f10-20020a05600c154a00b00401bdd749aemr8289510wmg.18.1700562286702; Tue, 21 Nov 2023 02:24:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/8] hw/arm/stm32f100: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:40 +0000 Message-Id: <20231121102441.3872902-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562373018100002 From: Philippe Mathieu-Daud=C3=A9 The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b284..a74d7b369c1 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) =20 struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; =20 - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9fb..b90d440d7aa 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } =20 -static Property stm32f100_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f100_soc_info =3D { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952fc..190db6118b9 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) =20 static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init =3D stm32vldiscovery_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) --=20 2.34.1