From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700562408; cv=none; d=zohomail.com; s=zohoarc; b=aTgBVdnFCAxPygKFsr5xf/jFgqev6xwb8gsA3KXO4ZRO3lLuWlUClfB1nXlwHnTeUKbZeAvaYG7tuyWTnswp0nHRwO3aqscz34Yf64SSM0Dy7VIYVqjQNSA0iTfSVk/mNq+v2T01QSlvyYfKP+fplmSv+H46KT2B2cw5an4BPIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700562408; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=48i16lN/X0IufQ0d/3ATpQbGOSnta9cBh6bFvGherhw=; b=X19UujhJauh4qKulrzr8Ax81dED3wyJIiQW73Og+fhYFbewdMD9WACgjfS4E9hLfXnwe/9sEIuEDTokA2Q3y0iSbvAHEUrp+nWDTB8qnMdiX3Xke3GFz6GvT+88WnptbcsFjp871YLp47aHQg15DfR6vjpA3sWkej3Cjk4Qfybk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700562408736345.3554043028313; Tue, 21 Nov 2023 02:26:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5Nw2-0004Ik-4Q; Tue, 21 Nov 2023 05:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5Nw0-0004G5-J7 for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5Nvx-0007EP-L2 for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-507a29c7eefso7630748e87.1 for ; Tue, 21 Nov 2023 02:24:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562284; x=1701167084; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=48i16lN/X0IufQ0d/3ATpQbGOSnta9cBh6bFvGherhw=; b=bsq+uaoAQ/OtEMEEvn+G2zO+g+3ZPjiMvYEakYfju3TYHWcupjVwJPyDuVWPI1PRMd k7QWCDQdtB2gpoMxxV9LLj3TecDBg5tNorCfr0AnZX9ABLaGoPRxEUQtYPRocWEXmLCu Jmn2WtyLzUlrQmL0SoHPVv27mQ900aTGN3ujWVQgJxtK7vbJWHhsBNAGZdUWwRBP80NJ gyC/jSagZHsSJ62EqFRFiYiGM2IxCjzkd2ixnJWmDNcEiUPlVqKStfAKEvhjUaJGSK9k Ztw2h0ge/EVmVbO/VID6Z7I1pHhKUVxkAPxD3E4Zzc7DRloJN5BGz4jwTvoLcrmXSMGl MEOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562284; x=1701167084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=48i16lN/X0IufQ0d/3ATpQbGOSnta9cBh6bFvGherhw=; b=BGIfFj6F2jFsopBToTCgaEFiKmPfe7jYTF1lDoxOakF8XQvGCPhNCrxlthAdHaAqol g6wANyUxN90lfpNvREbwneTHhYwyJxU9+hLXlccq3VJhihXP5HvrOB25SgrgPKYty0ic p7dohVj0BUrhfG33FZ70IJdEdV+0f9bTfUuUIx9+Af+a+EoAXU8DOG8c1ETyyg5y8893 Rt081Nj0kR8NhJYYXSJz2TCnuC1tEnJQPd4XccwUBf3UjZ2g1ds3S1iI7KdDGlPHUHgE jQ4h8hpgp7UibjBThEb/Hhsr88NORluIckQvefo6Uv+TP79QlnVPRfIHh/gWlpBnoNXU BUvQ== X-Gm-Message-State: AOJu0YzVR3BhnbknwWDNjKDuQljftH569cnD8KrfYUy/7kzZ+IjfWZsn V6eND4x9D7IVBcLzXKxqJfYqG2GpoGYK1Ql717A= X-Google-Smtp-Source: AGHT+IEokHooP/rHzOaIt2poO4Ams1GHQdUMwviHlyc5yxy4yZ6Xs25emQOzbhB2Cj7TtoM1/8KNtg== X-Received: by 2002:ac2:5df3:0:b0:502:fdca:2eaa with SMTP id z19-20020ac25df3000000b00502fdca2eaamr6882544lfq.52.1700562283905; Tue, 21 Nov 2023 02:24:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/8] target/arm: enable FEAT_RNG on Neoverse-N2 Date: Tue, 21 Nov 2023 10:24:34 +0000 Message-Id: <20231121102441.3872902-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562409617100001 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on Neoverse-N2. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Richard Henderson Message-id: 20231114103443.1652308-1-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 08db1dbcc74..fcda99e1583 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1018,7 +1018,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + cpu->isar.id_aa64isar0 =3D 0x1221111110212120ull; /* with Crypto and F= EAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700562403; cv=none; d=zohomail.com; s=zohoarc; b=TP8bPbbu9Hxl4bMgUB5HW/lTwQdQI6mSAJY3tx5BbionJqU9VROx2Ylp/F73oHP34qLpWeNzer9ARYmmeLGBRljC4nUC4x+A+c18grs2krnQoQZfEzQjN+lMknHLfM6jL8Xab4uqcOKqzIqiRllvjAnfzNC/34mgekRWNQJ6oo0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700562403; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=aWov8zdztLe0Jlc/lkRlL/DlbtZzkn3RPI3Q2gppqQQ=; b=TFnu3KYyQvNgKDbgYbFrJDkjr1MNvGVYC/OQ++zOq0cRFtPc3c7GBUXzv6eo9xHVHOetGmKZACPaqD59NSeuMAI3O4L5PfxUFB9LudPpKCtBaJZOz2KrggqdRS67RtUv3S+tps7FcAUdeutJcy64UAnoywsrvBu5GVTLUhlypCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700562403894450.02442231783164; Tue, 21 Nov 2023 02:26:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5Nw2-0004It-AW; Tue, 21 Nov 2023 05:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5Nw0-0004Hs-UZ for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5Nvy-0007EY-Ab for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-507b9408c61so7320261e87.0 for ; Tue, 21 Nov 2023 02:24:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562284; x=1701167084; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aWov8zdztLe0Jlc/lkRlL/DlbtZzkn3RPI3Q2gppqQQ=; b=vZysZ6HrwMn5/R4nwXCKDzQVbVLIsu3F3zzyP0Y1QUVWfMo5XP1sNMA+/US9/rMAVW pCOKRwpleOyT/0DSh0fKt3hyyhLIWFgd8oGqKjr923fBxT8r+rNNaXs+khduK1nAE2S0 Q+DTi8Ws8+w+GUlyoJqJL95kJKeTTiQTFM4MiwEKmhRRCj1KdnLPfhYVh/Lp1/mbchaG anjvLxCxfF7Hzv1ng1LaNxNuaLPwTmOfwkKuBL2Ey5LJkxMgGnNXwTMrIUD3tOHgSX0C GNLSz9ec8n82PjZSFftWaMS53HkKgMVtcdZ+cq7Y9FsiXDnwIQMTr1MYQaknrxzj/bsz b5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562284; x=1701167084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aWov8zdztLe0Jlc/lkRlL/DlbtZzkn3RPI3Q2gppqQQ=; b=FdAdVWFRLrzKyKLLcIMkbIs7gGtOy5jeKAlyUi+WU5WaFKCRQeH6/jg3kKGDNdT2Qi cSUAJCfw9IW+Q9p2cLAiUlz8GlWKXn6vHEecoqgpP3CHyAW0w9wM5ImjqXupIJys29FZ kOVxWHqlyPtOmxMGvgggJrBbk+dEjuG5vBUqrAQnR8lUhdcr6f55mZAavqVFE/55vupG YwSfFaDbM2bVQMkkamXjx7omo4XYiwD63wHokz4ClG7ipRiGOlu6qh+JMiDKbHV2NEcL 7u2fb80gZVzVKCnDJtyxwvKtp2mpQ2IOHv3IJ9g0y6SfB35C3IZaG3leICP1IDp9x8Rl YXzw== X-Gm-Message-State: AOJu0YxWCkbN1tdhhm+Jzze2JqWuqfR1ycvsBlSWNbcISebllLccHOQI D5waAYS6mte3WRr8XCaUSpm1ez2WRgEwpgj6+RE= X-Google-Smtp-Source: AGHT+IGdojh2d9ZIEFJfH8k4PXA0q7rCTshMtSqqw0leBD+w89+iA9AyflLwf6cIA7UMu361mEqZNA== X-Received: by 2002:a19:6747:0:b0:508:12f5:f808 with SMTP id e7-20020a196747000000b0050812f5f808mr7156884lfj.57.1700562284445; Tue, 21 Nov 2023 02:24:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/8] hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ Date: Tue, 21 Nov 2023 10:24:35 +0000 Message-Id: <20231121102441.3872902-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562405563100003 Content-Type: text/plain; charset="utf-8" From: Ben Dooks The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from ic{c,v}_fullprio_mask should technically also remove any bit above 7 as these are marked reserved (read 0) and should therefore should not be written as anything other than 0. This was noted during a run of a proprietary test system and discused on the mailing list [1] and initially thought not to be an issue due to RES0 being technically allowed to be written to and read back as long as the implementation does not use the RES0 bits. It is very possible that the values are used in comparison without masking, as pointed out by Peter in [2], if (cs->hppi.prio >=3D cs->icc_pmr_el1) may well do the wrong thing. Masking these values in ic{c,v}_fullprio_mask() should fix this and prevent any future problems with playing with the values. [1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html [2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html Signed-off-by: Ben Dooks Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d07b13eb270..ab1a00508e6 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -146,7 +146,7 @@ static uint32_t icv_fullprio_mask(GICv3CPUState *cs) * with the group priority, whose mask depends on the value of VBPR * for the interrupt group.) */ - return ~0U << (8 - cs->vpribits); + return (~0U << (8 - cs->vpribits)) & 0xff; } =20 static int ich_highest_active_virt_prio(GICv3CPUState *cs) @@ -803,7 +803,7 @@ static uint32_t icc_fullprio_mask(GICv3CPUState *cs) * with the group priority, whose mask depends on the value of BPR * for the interrupt group.) */ - return ~0U << (8 - cs->pribits); + return (~0U << (8 - cs->pribits)) & 0xff; } =20 static inline int icc_min_bpr(GICv3CPUState *cs) --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700562398; cv=none; d=zohomail.com; s=zohoarc; b=gRNsjihkD3datKPbp01CwtOCBRbR/O8S3+a3fUr3eztASI6FOWAsA7G2CdFv6Zx4M2lvRPCQDlgBSIuuYhIz0cha/+xx5v2THhtJScUoh79jKEnDWiPZaU2lJmcVKFUwxNqA1YBhaGOJbYlvlovQ8kmIVIWSqe/aSeZMtMLgK9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700562398; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=A5nZHFs8XfXA4eqiIcDiwItWSy8HHd+ABkoJYVnAfcE=; b=npe/SGSPEacnAJ7YhA7Ap+9D3tFgFDjxbcZQOs3PRIDO2xP0dH6vG/PfNXCEXBc40JEdBtua76V7Hnjng/jcN8/QzTWejU0iyhEBBNY5v1GLPOn9Lu/+uPs8o1L2DNshlfL+GV+sm2sVYTQH9vK/BN0mnhUtUeMUCUfinxj2Vrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170056239885950.82732116136265; Tue, 21 Nov 2023 02:26:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5Nw4-0004KN-2y; Tue, 21 Nov 2023 05:24:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5Nw0-0004Hq-Tb for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5Nvy-0007Ei-Kb for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:48 -0500 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2c875207626so35993311fa.1 for ; Tue, 21 Nov 2023 02:24:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562285; x=1701167085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=A5nZHFs8XfXA4eqiIcDiwItWSy8HHd+ABkoJYVnAfcE=; b=ZiEA5xMWL+V/DagdSUqluHyhViSQw9buv09cAZ6uIcm7b0JgldBDf+Cc0M2u9m9URy W+IepTKsSUk/EbnAw8BWzeEkRaCkEwyzeDLSHSaSLMT4tLS1ckDohqAc+gwpbvHwVxuS B2Cuvq3K6BhkkdV/bPXp4pG0KwtjCeo4ndRTklJVJu3vSgGisUML0DGgswSZ4ydvA6ir L57uu3U1jLPQPLPNttJqwhbB7Mf4QHlGur5Bxk9JAILAQHVFOzVIf91VzSVImeJVTqRG UxLnr7kQdmSWeeaKtUrCZXWD/9k8nQs6HAryd8iR1ck+bLJUn4PSVg5Gu7bC4mQzu5Z3 212g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562285; x=1701167085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A5nZHFs8XfXA4eqiIcDiwItWSy8HHd+ABkoJYVnAfcE=; b=Xt4zUZXYCQrIH870xU4o8w7a9d5i7LmEz/d1mljiNIhCP92zQ/+BoLzsFGhnC8COC6 rTVR8WmpASCxp1nMcAKJjRCuNTCkKT4uLO0o50LrNjGC80CJJeNWKchuSgv0lvDaRCIz J6lp+pnnCznIVvpWcJyHJ3KoPgaZkZ+VKzLU636pRqgfQZ0pn9KT3EbZUlbzG0+gfI59 Wg5uVANgKP169FsiSeOn9qhD4qCA0Eydy3BC1Q9gah0NBOYzZYK7x4FNEp/fOOJ8QIwy KYQ7eGAcKXb6n8h/ef3sZ5aTlIt9X7Sz6wDyUafRLvDRg1jKl2t/SEZTCLM/cTken30/ weTg== X-Gm-Message-State: AOJu0YxwkD79iR7nmB0N4iWC/eTPT+VjILhtCILJxo4JGtvT3fLFihc1 Qrx5NSvKS2JuLrbaSAN5IQrCQnHtaRSPijlvkAc= X-Google-Smtp-Source: AGHT+IFdotlzajEFXNGHKkcbuBHZhVggup+Jq+o3QbLTyB3ngPdKWTuWKaRiDUMEgJAJ6PlOQ1NQMA== X-Received: by 2002:a2e:9015:0:b0:2c8:3613:d071 with SMTP id h21-20020a2e9015000000b002c83613d071mr6949584ljg.36.1700562284935; Tue, 21 Nov 2023 02:24:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/8] target/arm: Fix SME FMOPA (16-bit), BFMOPA Date: Tue, 21 Nov 2023 10:24:36 +0000 Message-Id: <20231121102441.3872902-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562399421100001 From: Richard Henderson Perform the loop increment unconditionally, not nested within the predication. Cc: qemu-stable@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1985 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20231117193135.1180657-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 296826ffe6a..1ee2690ceb5 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1037,10 +1037,9 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void = *vzm, void *vpn, =20 m =3D f16mop_adj_pair(m, pcol, 0); *a =3D f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); - - col +=3D 4; - pcol >>=3D 4; } + col +=3D 4; + pcol >>=3D 4; } while (col & 15); } row +=3D 4; @@ -1073,10 +1072,9 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *= vzm, void *vpn, =20 m =3D f16mop_adj_pair(m, pcol, 0); *a =3D bfdotadd(*a, n, m); - - col +=3D 4; - pcol >>=3D 4; } + col +=3D 4; + pcol >>=3D 4; } while (col & 15); } row +=3D 4; --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700562378; cv=none; d=zohomail.com; s=zohoarc; b=SpYlVdnGcv9LBe3tbkzrKh4fD8e9AF560WoJh7pe2bYq1Yy/38HV82HYmP+LNbmRdqH67WQkcYtMsl1aM7Mmhj66dDJ0LXW+DfSVtCk+F2EqU75upq0qvS724kTtKz4ELExNu57OXP/bacM4AWLFmc2b2mwAQoOhk7pXHlB1i28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700562378; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DFKuHjN+ndUlQFTqRBZjDt9iBODNYrCuBl0JQxBqPME=; b=nrQ7zA5AdafnwebdOpiak9HALetA619EdvAbdFHeL2E31dche0ZT8EPowmR58MLswrtzDznmjxWcJOjWHMjUH6YzVOxm+j8gn9xnuU1qX2uM3VOBw4h2XSPX/WHPgn/y1tu8bAiwNExdzSbjl4bdXT8jIK9Mg+teNxesl/Ml3zg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170056237833583.43684773722646; Tue, 21 Nov 2023 02:26:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5Nw6-0004Lw-Cp; Tue, 21 Nov 2023 05:24:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5Nw1-0004Il-TZ for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:49 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5Nvz-0007Em-0z for qemu-devel@nongnu.org; Tue, 21 Nov 2023 05:24:49 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4083ac51d8aso24019515e9.2 for ; Tue, 21 Nov 2023 02:24:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562285; x=1701167085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DFKuHjN+ndUlQFTqRBZjDt9iBODNYrCuBl0JQxBqPME=; b=TPXj3r9ueDfXtQDyIuWUFvdMPjoqBf6MZQp33VXNKzOYVGdh4q9JSZULgZYJtEV0K2 Q6+u2/DRYTzyDmPZtJy23tIZesRqYnadAGJVvN3OzfhpQkeuG2OVzE+QJPSw48n+zkuH mq1j/P6Ek7QsVVsHWGU0yGPqfHpFbXI8AgPAbjkQhUIC4nH/YQ3JVwROa7qFiP3CpHKH wV1cS0FL5rMAASCzkNKcUGuSIbSHzshnOVBxGaVMlbxorFwkB+I71QxhNXYlaR+2nIZX K+CyOan+hZX2njH5rY+9BmDwnUvDnUp/itHFpRVeVts0h+eh3TdLJJhvIac2wxfCAPOM I5EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562285; x=1701167085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DFKuHjN+ndUlQFTqRBZjDt9iBODNYrCuBl0JQxBqPME=; b=DMelyUGDo871MzFys5BYcLanxT1E8Synhzj+QCEmuhKNwqOchR9G9iwXWRk30uFbvF pyvhIMYpY5SuFzbt3K6Sk3fX10Xs2ZopHEEpeYV8czYjYKjg1uaKhrjkEGqJziERE0kF ClZUj/mJu/Z4/GAp+lPtm5ieP2jF7tvmNrn0NLQt400yXNii7ZhhKsRX79D7b5yl20af vX2L46tYhP+527cE90oA0in5Sv+U4RDSOcyE5AT0meMHtZQq8UDQMw86abj3C9DL1jfM PC53kFQzgmHiw35L4KZJnpOpJjblgWz6ZD0hlxxH/sGvuqcY/cFtPVBLwd6rVZWBSzbO chNA== X-Gm-Message-State: AOJu0YxYv4ftL5Bg7nX8GqwDe7Mwgx6rNFxe9JXkEaKcCZXsM99wP17C TTxO8ELbJ1H9zKE1W+V8GKmBTammOGjMnnrrHcU= X-Google-Smtp-Source: AGHT+IHDe4bzKtVWfo7+7Vw51BGUaLqj/+w2fVVpgJw5pAybW5CU1ClQk2HoOyQ6doUkD1BmIKQZAw== X-Received: by 2002:a05:600c:3b84:b0:40b:2b86:c886 with SMTP id n4-20020a05600c3b8400b0040b2b86c886mr442704wms.31.1700562285364; Tue, 21 Nov 2023 02:24:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/8] hw/core/machine: Constify MachineClass::valid_cpu_types[] Date: Tue, 21 Nov 2023 10:24:37 +0000 Message-Id: <20231121102441.3872902-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562379071100001 From: Gavin Shan Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20231117071704.35040-2-philmd@linaro.org [PMD: Constify HPPA machines, restrict valid_cpu_types to machine_class_init() handlers] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/hw/boards.h | 2 +- hw/hppa/machine.c | 22 ++++++++++------------ hw/m68k/q800.c | 11 +++++------ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index a7359992980..da85f86efb9 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -273,7 +273,7 @@ struct MachineClass { bool has_hotpluggable_cpus; bool ignore_memory_transaction_failures; int numa_mem_align_shift; - const char **valid_cpu_types; + const char * const *valid_cpu_types; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 9d08f39490e..c8da7c18d53 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Erro= r **errp) } } =20 -static const char *HP_B160L_machine_valid_cpu_types[] =3D { - TYPE_HPPA_CPU, - NULL -}; - static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + TYPE_HPPA_CPU, + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); NMIClass *nc =3D NMI_CLASS(oc); =20 mc->desc =3D "HP B160L workstation"; mc->default_cpu_type =3D TYPE_HPPA_CPU; - mc->valid_cpu_types =3D HP_B160L_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_B160L_init; mc->reset =3D hppa_machine_reset; mc->block_default_type =3D IF_SCSI; @@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = =3D { }, }; =20 -static const char *HP_C3700_machine_valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, - NULL -}; - static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + TYPE_HPPA64_CPU, + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); NMIClass *nc =3D NMI_CLASS(oc); =20 mc->desc =3D "HP C3700 workstation"; mc->default_cpu_type =3D TYPE_HPPA64_CPU; - mc->valid_cpu_types =3D HP_C3700_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_C3700_init; mc->reset =3D hppa_machine_reset; mc->block_default_type =3D IF_SCSI; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 1d7cd5ff1c3..83d1571d02f 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] =3D { }; static const size_t hw_compat_q800_len =3D G_N_ELEMENTS(hw_compat_q800); =20 -static const char *q800_machine_valid_cpu_types[] =3D { - M68K_CPU_TYPE_NAME("m68040"), - NULL -}; - static void q800_machine_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + M68K_CPU_TYPE_NAME("m68040"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Macintosh Quadra 800"; mc->init =3D q800_machine_init; mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); - mc->valid_cpu_types =3D q800_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->max_cpus =3D 1; mc->block_default_type =3D IF_SCSI; mc->default_ram_id =3D "m68k_mac.ram"; --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700562313; cv=none; d=zohomail.com; s=zohoarc; b=Bp7jYyumanFB6lCfMmdCqkDDOEH9porzy+QTes/Vw1rM2XHqX0cgOrCWxGs6BuHX/fo5wnjpFMYI06lvV1wieF83Wo/vakfsGA0YKUQT3rzu6FwxPQVfaHO2PJjBWHGUY/VU70xJBxTdu1xaIwHnd0x+c2Aqqp/0zLXW7kxOc8w= ARC-Message-Signature: i=1; a=rsa-sha256; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562285; x=1701167085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=O+zUt/QLfrTlh2hm/zQQFNIIEpKPbEpTMNRg+Stq7bo=; b=VvvXWgFS76oudZdMVi6VAcixHNXNTgaNFeMY6U2ZDpMULYs+8FgtqMWhtWLPKa+YeX /5kG25G9framYUARbPwp7pU+WuRElNPWlBeb6Ixt6iSvh3XJVBrCYEwS3pKb2JLQCHa6 DyckOfWOh5jwXvVWA5Xw5Kzethj6StGW6eFPpCmBT1XPJWaHEJyd7s3w9KU9u5Qf3b52 sbGZGr5K5ps4seKdjRCIvhZsi3IOHcKS8Jbe7mKJnzyseuJ0Ggg2L9EysJEkhVoIWnWJ 3Fw52h7K1S//ZG+F9vF0FZpMVrakzCMiOrDuiT7vl6VhsdmcZjuT09qQOMUG4FaeOpB3 Ixdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562285; x=1701167085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O+zUt/QLfrTlh2hm/zQQFNIIEpKPbEpTMNRg+Stq7bo=; b=NdP3eUfoAFKpCh77zMuG77WmDFkSeZBYlqvadwOJrX/WFIPYNX7M2zwggDK/8hnnD7 En2TclYM8ub6PT2+h+sFm1Rvg8adsLgs5MdUwkb/N2tBKUK1zXe+zlxR3IMk/dbDujAG y6a/jTuSwWP9K5kkpA6bdLS+r0dMTM9vRDf/uAO9sjXR74zaixLkvCtcMjPoj+dly3Es Jk9E6DwICwKiTMKFk1DMfTwQ7YDZH5uikaOANTxQMiA8POAwgezcXcjNuLMn5PBblDvU p0/zeLLZdCTUVf3OHT7bJCcG0c1aJ5CFSyGhg93jpMi7Aud0XVdcjoR089fLMvnZI/ka w/pw== X-Gm-Message-State: AOJu0YwGed0eV0Z+nhKMtJLPG/OGfmE9IjIfTmP3qnGDntoSr0nOnbRp 7oLJhxogi7YQc47QvZScyo6RK2aCLST1eKpBJKE= X-Google-Smtp-Source: AGHT+IGQsuYSj+84f0d6GT2O1pPlJbJ7zfB1MGwHTZhaFPBhfCjIwfXTv5fagvuxpX3kkJbyFUaMFg== X-Received: by 2002:a05:600c:1394:b0:409:5d7d:b26d with SMTP id u20-20020a05600c139400b004095d7db26dmr7014234wmf.15.1700562285768; Tue, 21 Nov 2023 02:24:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/8] hw/arm/stm32f405: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:38 +0000 Message-Id: <20231121102441.3872902-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562314181100001 From: Philippe Mathieu-Daud=C3=A9 Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-3-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f405_soc.h | 4 ---- hw/arm/netduinoplus2.c | 7 ++++++- hw/arm/olimex-stm32-h405.c | 8 ++++++-- hw/arm/stm32f405_soc.c | 8 +------- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab23..d15c03c4b5d 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) =20 struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; =20 ARMv7MState armv7m; =20 diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c0816054..2e589849478 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) =20 static void netduinoplus2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc =3D "Netduino Plus 2 Machine (Cortex-M4)"; mc->init =3D netduinoplus2_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b75..d793de7c97f 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) =20 static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc =3D "Olimex STM32-H405 (Cortex-M4)"; mc->init =3D olimex_stm32_h405_init; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types =3D valid_cpu_types; =20 /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size =3D 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee41..a65bbe298d2 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,= Error **errp) =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } =20 -static Property stm32f405_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ } =20 --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562286; x=1701167086; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oiUnhyvPvuaZLFK9pIShm6X1qmnlGPN+kB6sEamcCNk=; b=rcfTl/iaDNjpihlRNQ4ocO9Ahzsd3fZnvfeNnCA5l/YiTzQdN5yLKqeeHl/A1PGdpK 8DCG4IuEVcPcWhVWXCGS25NywOUwKgFgVkOWIUQMaHEtGjMGMXrOrVi8ea4rHKp0VbyF c4Kkv2pWumZcKq4J9saAEyuHgedTV5cnRz20IOP8acWXl4jI9R7BBQQl+ci8d53wtP/Y 7N1kd/5AXdNCHYP9LMrgbIIGYfhcILuI3KsBNrU1idEJTg7h4H6jnOK9hbFIXU57PFG3 fQWMf0nQUmCy7BvdjbmHvqUx+XY9+wTMdozk+IY4oQyelW6YoGtALEsiQdaCZFDjf6mM i9UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562286; x=1701167086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oiUnhyvPvuaZLFK9pIShm6X1qmnlGPN+kB6sEamcCNk=; b=o8hAnITgdImSGXUFsetMFXb/vbof3LoNLK6RTXCmOT6+v/738rn3MaqZLM5MFZpwUp ORMH+a8kHTJ57+njm9Vgf+lBvyKdkEv6E5k8fKkUKGnx3wGfQb2P1wlWfTweYYQgWJwZ HZhC7GxTWqJJYiEYkOBJxRlCh7EosoRfhtTZ0fpaQWqUxuQsrpIGkJVdH3lv/TqtxKYy XspguM+Ya5dsSG4p8itGNtAVplupQP3LzRmpTHrmb0Yp0wo/dwJTDhNWXPYGwiBalPko 6mG69b8ti2XKzdkwSBQsBIvzMAvI5tPmGjyVkAYxbV4cGY5pJbQjNUtpXjyYCO/7bYwH A2Fg== X-Gm-Message-State: AOJu0YwVtER4rWMgG0YX0QjFJqyIoRcXBjGvwsyAXV8/qM4gaZlbTVpH 2GvvR1mzHY3eNipoQaK4hjz/9SA4TDb43BBy2RU= X-Google-Smtp-Source: AGHT+IG5OGgcAvB+6DAJwv2fawesGqN+7unFSCk+AMwp5lwyKRZJErnGX5a20HK/6hVxXmFRLmXWgA== X-Received: by 2002:a05:600c:5489:b0:405:784a:d53e with SMTP id iv9-20020a05600c548900b00405784ad53emr1722310wmb.20.1700562286267; Tue, 21 Nov 2023 02:24:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/8] hw/arm/stm32f205: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:39 +0000 Message-Id: <20231121102441.3872902-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562373016100001 From: Philippe Mathieu-Daud=C3=A9 The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-4-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f205_soc.h | 4 ---- hw/arm/netduino2.c | 7 ++++++- hw/arm/stm32f205_soc.c | 9 ++------- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 5a4f7762642..4f4c8bbebc1 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC) #define SRAM_SIZE (128 * 1024) =20 struct STM32F205State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; =20 ARMv7MState armv7m; =20 diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 83753d53a3f..501f63a77f9 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F205_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine) =20 static void netduino2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "Netduino 2 Machine (Cortex-M3)"; mc->init =3D netduino2_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->ignore_memory_transaction_failures =3D true; } =20 diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index c6b75a381d9..1a548646f6e 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_so= c, Error **errp) } } =20 -static Property stm32f205_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f205_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f205_soc_realize; - device_class_set_props(dc, stm32f205_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f205_soc_info =3D { --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562287; x=1701167087; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fwjCpEg7CxgIC61BgitQvtOo2gBc/4p1x2tjHLKtQjw=; b=CmYlSFp++lMA0x15vbqc9mWYeKDmgQs+BgJwf+XhTA3g5D3rrCgcAk8SHTbpOxFR7S eYwABQLGyha6vSVLz61kVhYI3faIudkvYLSrISJ95wSB+7AUThgaYQNQs9GAmxB4hg0a qnVxqwZQUg86OMEK2Ggsz81fokRM1k1D85s1oq+YwcefDce9hGjkq2tuJN1KKbSKGjTZ y7lS9xBBDgPhvsrmeRfOd3CNH7epiPAcDimxH3rNiESSUyQDkVtnMUw3NZoPQjDqWMMj S6OIpXZUCv3gi1TNmauZNafM6JCEc3Yz99p5W/avsVfkFBAxhY3TM7VyN+84shzOpCpu MtXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562287; x=1701167087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwjCpEg7CxgIC61BgitQvtOo2gBc/4p1x2tjHLKtQjw=; b=N4HGpXi0CJSUfEGVAscqjQHeSaabglt1M33V5nNIGk75mWfCUyMTvSX/9tipfOrdSt ar2Or2mZS0U1uVZCwgFr9C67gAk52xv6PT74GwwdiAmrhebZLW71hL3TJb4gDKfLk4MX WDVdQbwItSD8ZkAWyhGdsI3yEib4LijeJfLC/tevQFvxKC4y7joN9LwV4ptqmBq9ygR5 jYs0QTlnANkzpOd48NFfY4hW8f3QKX0MloPywyIW+K3gqIDwPccEafSOHFv3JajGc91L q70qP8PlPudbQ9WA0MdaMFYlHUk4+7vDH/FWumjRrduYicMZosZPQKbfTOisDbrZOsPG l3sQ== X-Gm-Message-State: AOJu0YwWctFWvYUqapw0hhwrunaMML7NsvKX6K7SnXmvEaWByQBLijWR psd/4vf++1hd+FlS9SVQLECciAqHILj51FH+fjg= X-Google-Smtp-Source: AGHT+IG8iFFMOe6HPUsEOmnw52AXUg8wZ65gsfaIuH5vtX1PwziiJPlqDvFOj6eHvHe86soLjl042A== X-Received: by 2002:a05:600c:154a:b0:401:bdd7:49ae with SMTP id f10-20020a05600c154a00b00401bdd749aemr8289510wmg.18.1700562286702; Tue, 21 Nov 2023 02:24:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/8] hw/arm/stm32f100: Report error when incorrect CPU is used Date: Tue, 21 Nov 2023 10:24:40 +0000 Message-Id: <20231121102441.3872902-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562373018100002 From: Philippe Mathieu-Daud=C3=A9 The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan Message-id: 20231117071704.35040-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b284..a74d7b369c1 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) =20 struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; =20 - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9fb..b90d440d7aa 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } =20 -static Property stm32f100_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f100_soc_info =3D { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952fc..190db6118b9 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) =20 static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init =3D stm32vldiscovery_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) --=20 2.34.1 From nobody Wed Nov 27 04:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c181900b00405442edc69sm20450835wmp.14.2023.11.21.02.24.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 02:24:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700562287; x=1701167087; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uKQw+Bk5quR0x5DmJj6cUhmxTm7kP9pkGDcsohAx+Rw=; b=qlDE5VNqkspa2ktpqDG357XZ1KO9wJXPcJ0wIyeBiaoQNz/X/kqsYdHhIxNhbTOqrm 6PJvX/PO+vmKEKZMxMTCpCxsVaSvEKb6J31xfDpCaQxVzhrxUQ/pWK/+ABgwUCWwRyy7 3VBydexpiTS2IXqWVLWtgcCfCG3KZhfPQMrP5JPzVMXWZA/xiDRxkG01VVcMRTSh1ec8 snvKiKDpr8RO7EnObYKbxUPrRpweUgHzWZLls8AOkJa0vny+DpEMTafCX57p+C1ayYXy 5kqq6inmmE4c03CsDSqEFe6KRQmQj45Q5VCDWBTAaaYnz6cHxVM8DK0tIp0jwMvnHaFL 2iOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700562287; x=1701167087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uKQw+Bk5quR0x5DmJj6cUhmxTm7kP9pkGDcsohAx+Rw=; b=m/CwxQDIn1X/EBl3Xw7zROBl3lKmUq6A7VzNU81zZUBTzWd19ggkF66Ipa7+R0zDV5 wT8gsfGvRcv0gOoKI05C72306eBQhH+HyQ5ihVYYeJXQJywpFAssVIe2Kw6Vj3JasK2E J8+i8YKoi7AhTtgiQWUMLPCiRJDb8DFB9jhsNe9Z81DaUqrqWtlHQJaErJjHU7gH9e+f HfbSAqDTAVefvzAQMJcVGY5bfo2A5UGwM8JYf1+m9wcH0mkTexVKedITWISvVASy5ABC NkripJlNHiOzZMrqFkUuvUKGCDBwQZ/DSYtA5jH3donHAtXNXOpDESsPnK+lZaLOrx+H l44A== X-Gm-Message-State: AOJu0Yy4TrHs7fWjXjdL7Msqjuh1i82bgCw3N2CkGZFCBOM+KVoqEaja 6eIuatzVrQvv3f8a37mFZkc6WbX6P2iLVCZlGug= X-Google-Smtp-Source: AGHT+IFjBETApgksxp/2EPadPF/r/SIeNU1JmXH3zfQtc3MKrbloBbeKn4BdSs9USXAJdZHjAsaSrw== X-Received: by 2002:a2e:9217:0:b0:2c7:f9d:587c with SMTP id k23-20020a2e9217000000b002c70f9d587cmr6370929ljg.24.1700562287146; Tue, 21 Nov 2023 02:24:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 8/8] hw/arm/fsl-imx: Do not ignore Error argument Date: Tue, 21 Nov 2023 10:24:41 +0000 Message-Id: <20231121102441.3872902-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231121102441.3872902-1-peter.maydell@linaro.org> References: <20231121102441.3872902-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700562387142100003 From: Philippe Mathieu-Daud=C3=A9 Both i.MX25 and i.MX6 SoC models ignore the Error argument when setting the PHY number. Pick &error_abort which is the error used by the i.MX7 SoC (see commit 1f7197deb0 "ability to change the FEC PHY on i.MX7 processor"). Fixes: 74c1330582 ("ability to change the FEC PHY on i.MX25 processor") Fixes: a9c167a3c4 ("ability to change the FEC PHY on i.MX6 processor") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20231120115116.76858-1-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 3 ++- hw/arm/fsl-imx6.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 24c43745903..9aabbf7f587 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -169,7 +169,8 @@ static void fsl_imx25_realize(DeviceState *dev, Error *= *errp) epit_table[i].irq)); } =20 - object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err); + object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, + &error_abort); qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) { diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 4fa7f0b95ed..7dc42cbfe64 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -379,7 +379,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) spi_table[i].irq)); } =20 - object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); + object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, + &error_abort); qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { return; --=20 2.34.1