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Mon, 20 Nov 2023 23:51:57 +0000 Received: from smtpav06.dal12v.mail.ibm.com (smtpav06.dal12v.mail.ibm.com [10.241.53.105]) by smtprelay03.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3AKNpvlt19726992 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 20 Nov 2023 23:51:57 GMT Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1FEF258055; Mon, 20 Nov 2023 23:51:57 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DEABA58043; Mon, 20 Nov 2023 23:51:56 +0000 (GMT) Received: from mamboa4.aus.stglabs.ibm.com (unknown [9.3.84.87]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 23:51:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=FA/WKiC0ycH1RIoOxSB5458KHGmuWPjOTV0LbnFNOgk=; b=TvpCwKSWyDfJ2sQ+4Fpg0j0t/4akSlr4GLjbIJ2I5kv83JcgUvvxqEP7pubRlvYrNhBN kI4H+YRbvtoLFRqglmZfvNeujhGlMFCZm1Bvu8buLULfHC1WCw2DNwdo/9gHS+lZldFm QGk/1YSbGyZt7hY05Nn5ELQ2XwKuLePP4j7P4ivAP9xq/MP8O84at5johNYVkOYgiZlx kU6da3dj1NddhFEIqljrYA+yww/s9aBXpTJ24FnTcN/SeyQGmZhlvwyuXBKrI5Fw/Qzw N+jsAq+XtJ7xV2AVHuGh/BtI1T0mwM767EEZhuS3TiinLRfS5ZhuLMyZ86I4lUFAvU4I 1g== From: Glenn Miles To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Glenn Miles , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Andrew Jeffery Subject: [PATCH v4 02/11] misc/pca9552: Let external devices set pca9552 inputs Date: Mon, 20 Nov 2023 17:51:03 -0600 Message-Id: <20231120235112.1951342-3-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231120235112.1951342-1-milesg@linux.vnet.ibm.com> References: <20231120235112.1951342-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 1oNUyJ_pekz74drkL6163t7yNTjFlIGw X-Proofpoint-ORIG-GUID: oR_v59TBQZTUtuvPCsEwmKczKjSgyLqR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_22,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200175 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1700524358474100007 Content-Type: text/plain; charset="utf-8" Allow external devices to drive pca9552 input pins by adding input GPIO's to the model. This allows a device to connect its output GPIO's to the pca9552 input GPIO's. In order for an external device to set the state of a pca9552 pin, the pin must first be configured for high impedance (LED is off). If the pca9552 pin is configured to drive the pin low (LED is on), then external input will be ignored. Here is a table describing the logical state of a pca9552 pin given the state being driven by the pca9552 and an external device: PCA9552 Configured State | Hi-Z | Low | ------+------+-----+ External Hi-Z | Hi | Low | Device ------+------+-----+ State Low | Low | Low | ------+------+-----+ Reviewed-by: Andrew Jeffery Signed-off-by: Glenn Miles --- No changes from previous version hw/misc/pca9552.c | 50 +++++++++++++++++++++++++++++++++------ include/hw/misc/pca9552.h | 3 ++- 2 files changed, 45 insertions(+), 8 deletions(-) diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c index 445f56a9e8..fe876471c8 100644 --- a/hw/misc/pca9552.c +++ b/hw/misc/pca9552.c @@ -44,6 +44,8 @@ DECLARE_CLASS_CHECKERS(PCA955xClass, PCA955X, #define PCA9552_LED_OFF 0x1 #define PCA9552_LED_PWM0 0x2 #define PCA9552_LED_PWM1 0x3 +#define PCA9552_PIN_LOW 0x0 +#define PCA9552_PIN_HIZ 0x1 =20 static const char *led_state[] =3D {"on", "off", "pwm0", "pwm1"}; =20 @@ -110,22 +112,27 @@ static void pca955x_update_pin_input(PCA955xState *s) =20 for (i =3D 0; i < k->pin_count; i++) { uint8_t input_reg =3D PCA9552_INPUT0 + (i / 8); - uint8_t input_shift =3D (i % 8); + uint8_t bit_mask =3D 1 << (i % 8); uint8_t config =3D pca955x_pin_get_config(s, i); + uint8_t old_value =3D s->regs[input_reg] & bit_mask; + uint8_t new_value; =20 switch (config) { case PCA9552_LED_ON: /* Pin is set to 0V to turn on LED */ - qemu_set_irq(s->gpio[i], 0); - s->regs[input_reg] &=3D ~(1 << input_shift); + s->regs[input_reg] &=3D ~bit_mask; break; case PCA9552_LED_OFF: /* * Pin is set to Hi-Z to turn off LED and - * pullup sets it to a logical 1. + * pullup sets it to a logical 1 unless + * external device drives it low. */ - qemu_set_irq(s->gpio[i], 1); - s->regs[input_reg] |=3D 1 << input_shift; + if (s->ext_state[i] =3D=3D PCA9552_PIN_LOW) { + s->regs[input_reg] &=3D ~bit_mask; + } else { + s->regs[input_reg] |=3D bit_mask; + } break; case PCA9552_LED_PWM0: case PCA9552_LED_PWM1: @@ -133,6 +140,12 @@ static void pca955x_update_pin_input(PCA955xState *s) default: break; } + + /* update irq state only if pin state changed */ + new_value =3D s->regs[input_reg] & bit_mask; + if (new_value !=3D old_value) { + qemu_set_irq(s->gpio_out[i], !!new_value); + } } } =20 @@ -340,6 +353,7 @@ static const VMStateDescription pca9552_vmstate =3D { VMSTATE_UINT8(len, PCA955xState), VMSTATE_UINT8(pointer, PCA955xState), VMSTATE_UINT8_ARRAY(regs, PCA955xState, PCA955X_NR_REGS), + VMSTATE_UINT8_ARRAY(ext_state, PCA955xState, PCA955X_PIN_COUNT_MAX= ), VMSTATE_I2C_SLAVE(i2c, PCA955xState), VMSTATE_END_OF_LIST() } @@ -358,6 +372,7 @@ static void pca9552_reset(DeviceState *dev) s->regs[PCA9552_LS2] =3D 0x55; s->regs[PCA9552_LS3] =3D 0x55; =20 + memset(s->ext_state, PCA9552_PIN_HIZ, PCA955X_PIN_COUNT_MAX); pca955x_update_pin_input(s); =20 s->pointer =3D 0xFF; @@ -380,6 +395,26 @@ static void pca955x_initfn(Object *obj) } } =20 +static void pca955x_set_ext_state(PCA955xState *s, int pin, int level) +{ + if (s->ext_state[pin] !=3D level) { + uint16_t pins_status =3D pca955x_pins_get_status(s); + s->ext_state[pin] =3D level; + pca955x_update_pin_input(s); + pca955x_display_pins_status(s, pins_status); + } +} + +static void pca955x_gpio_in_handler(void *opaque, int pin, int level) +{ + + PCA955xState *s =3D PCA955X(opaque); + PCA955xClass *k =3D PCA955X_GET_CLASS(s); + + assert((pin >=3D 0) && (pin < k->pin_count)); + pca955x_set_ext_state(s, pin, level); +} + static void pca955x_realize(DeviceState *dev, Error **errp) { PCA955xClass *k =3D PCA955X_GET_CLASS(dev); @@ -389,7 +424,8 @@ static void pca955x_realize(DeviceState *dev, Error **e= rrp) s->description =3D g_strdup("pca-unspecified"); } =20 - qdev_init_gpio_out(dev, s->gpio, k->pin_count); + qdev_init_gpio_out(dev, s->gpio_out, k->pin_count); + qdev_init_gpio_in(dev, pca955x_gpio_in_handler, k->pin_count); } =20 static Property pca955x_properties[] =3D { diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index b6f4e264fe..c36525f0c3 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -30,7 +30,8 @@ struct PCA955xState { uint8_t pointer; =20 uint8_t regs[PCA955X_NR_REGS]; - qemu_irq gpio[PCA955X_PIN_COUNT_MAX]; + qemu_irq gpio_out[PCA955X_PIN_COUNT_MAX]; + uint8_t ext_state[PCA955X_PIN_COUNT_MAX]; char *description; /* For debugging purpose only */ }; =20 --=20 2.31.1