From nobody Wed Nov 27 06:50:07 2024 Delivered-To: importer@patchew.org Received-SPF: none (zohomail.com: 8.43.85.245 is neither permitted nor denied by domain of lists.libvirt.org) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; spf=none (zohomail.com: 8.43.85.245 is neither permitted nor denied by domain of lists.libvirt.org) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1700494594952121.28051685927699; Mon, 20 Nov 2023 07:36:34 -0800 (PST) Received: by lists.libvirt.org (Postfix, from userid 996) id C614718E1; Mon, 20 Nov 2023 10:36:33 -0500 (EST) Received: from lists.libvirt.org (localhost [IPv6:::1]) by lists.libvirt.org (Postfix) with ESMTP id 53A041924; Mon, 20 Nov 2023 10:10:51 -0500 (EST) Received: by lists.libvirt.org (Postfix, from userid 996) id BF80F1859; Mon, 20 Nov 2023 10:08:54 -0500 (EST) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id A40AF17C5 for ; Mon, 20 Nov 2023 10:08:47 -0500 (EST) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-40a46ea95f0so19077305e9.2 for ; Mon, 20 Nov 2023 07:08:47 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id b11-20020a05600010cb00b00332c0d256c5sm6570827wrx.80.2023.11.20.07.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 07:08:42 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 0279F655DF; Mon, 20 Nov 2023 15:08:35 +0000 (GMT) X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.4 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700492926; x=1701097726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I9723xBaPChd48Q2Z6VrVXqqZ/PYaPzTSFScKX3Q69c=; b=AmzbNoIfqXsHymZfxGNhS60nfWpUtm1e5pju632AWhLXpUkB8ztuhl16k3TCwOFMNR N95wHKEVwZu80S8WycmQFOfEee1rOk3MTpeFH8Q8YqQHSlp0dhjfysjpp9DoEMDoDM7c xbD0erXuciF/hPxCGUYRtmsPvAIGbJMu8oVnMNWeVpCQgxNu8/ZBRKx+gRRGE/6r4UWr Or16pzIzXKBQXyS0eA2sn8gIvluMTD4JTLj5I3u8SCnPCJ11hLGsYsnz6IYA3dpwS87G 2nNlTuVcCgYDJqc7qNAt8WNeJVa8He+5tLpuuW4Mo1MiFCtffJdRCouwUMBmLlntupCc 3COQ== X-Gm-Message-State: AOJu0YzyCI/Mb4ineblwX2844QjvBnMneGFlunyBcqLWMLaaT+dmqxGc BTz7ONuBiJSWhGd4UmwWxDKq5Q== X-Google-Smtp-Source: AGHT+IEW7RMJwGLr87ADHMs2b6yOzpNnUGuakZWs8wVeD9lyvE06mI+6Ofa+E8vaaSgh9dgZGPV2dg== X-Received: by 2002:a05:600c:3ba2:b0:3fe:1b4e:c484 with SMTP id n34-20020a05600c3ba200b003fe1b4ec484mr6461662wms.5.1700492926286; Mon, 20 Nov 2023 07:08:46 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v2 11/14] tests/tcg: enable arm softmmu tests Date: Mon, 20 Nov 2023 15:08:30 +0000 Message-Id: <20231120150833.2552739-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120150833.2552739-1-alex.bennee@linaro.org> References: <20231120150833.2552739-1-alex.bennee@linaro.org> MIME-Version: 1.0 Message-ID-Hash: LIYWLA2ISPWSQCTMYE6VHXEHXD6CI2ND X-Message-ID-Hash: LIYWLA2ISPWSQCTMYE6VHXEHXD6CI2ND X-MailFrom: alex.bennee@linaro.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Wainer dos Santos Moschetta , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Peter Maydell , David Hildenbrand , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, Beraldo Leal , qemu-arm@nongnu.org, devel@lists.libvirt.org, qemu-ppc@nongnu.org, Daniel Henrique Barboza , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexandre Iooss , Marek Vasut , Thomas Huth , Chris Wulff , Ilya Leoshkevich , Richard Henderson , Nicholas Piggin X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1700494596057100001 To make it easier to test 32 bit Arm softmmu issues implement a basic boot.S so we can build the multiarch tests. Currently CHECK_UNALIGNED is disabled as I haven't got the right magic set for it to work. Message-Id: <20231115205542.3092038-10-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - use endf macro for global function symbols in boot.S --- tests/tcg/arm/Makefile.softmmu-target | 64 +++++- tests/tcg/arm/system/boot.S | 301 ++++++++++++++++++++++++++ tests/tcg/arm/system/kernel.ld | 24 ++ 3 files changed, 379 insertions(+), 10 deletions(-) create mode 100644 tests/tcg/arm/system/boot.S create mode 100644 tests/tcg/arm/system/kernel.ld diff --git a/tests/tcg/arm/Makefile.softmmu-target b/tests/tcg/arm/Makefile= .softmmu-target index 7857ab9324..aadc12767e 100644 --- a/tests/tcg/arm/Makefile.softmmu-target +++ b/tests/tcg/arm/Makefile.softmmu-target @@ -8,20 +8,64 @@ ARM_SRC=3D$(SRC_PATH)/tests/tcg/arm/system # Set search path for all sources VPATH +=3D $(ARM_SRC) =20 -ARM_TESTS=3Dtest-armv6m-undef +# Specific Test Rules =20 -TESTS +=3D $(ARM_TESTS) +test-armv6m-undef: test-armv6m-undef.S + $(CC) -mcpu=3Dcortex-m0 -mfloat-abi=3Dsoft \ + -Wl,--build-id=3Dnone -x assembler-with-cpp \ + $< -o $@ -nostdlib -N -static \ + -T $(ARM_SRC)/$@.ld =20 -LDFLAGS+=3D-nostdlib -N -static +run-test-armv6m-undef: QEMU_OPTS+=3D-semihosting -M microbit -kernel =20 -%: %.S %.ld - $(CC) $(CFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_S= RC)/$@.ld +ARM_TESTS+=3Dtest-armv6m-undef =20 -# Specific Test Rules +# These objects provide the basic boot code and helper functions for all t= ests +CRT_OBJS=3Dboot.o =20 -test-armv6m-undef: EXTRA_CFLAGS+=3D-mcpu=3Dcortex-m0 -mfloat-abi=3Dsoft -W= l,--build-id=3Dnone -x assembler-with-cpp +ARM_TEST_SRCS=3D$(wildcard $(ARM_SRC)/*.c) +ARM_TESTS+=3D$(patsubst $(ARM_SRC)/%.c, %, $(ARM_TEST_SRCS)) =20 -run-test-armv6m-undef: QEMU_OPTS+=3D-semihosting -M microbit -kernel +CRT_PATH=3D$(ARM_SRC) +LINK_SCRIPT=3D$(ARM_SRC)/kernel.ld +LDFLAGS=3D-Wl,-T$(LINK_SCRIPT) +CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) +LDFLAGS+=3D-static -nostdlib -N $(CRT_OBJS) $(MINILIB_OBJS) -lgcc + +# building head blobs +.PRECIOUS: $(CRT_OBJS) + +%.o: $(ARM_SRC)/%.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@ + +# Build and link the tests +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + +memory: CFLAGS+=3D-DCHECK_UNALIGNED=3D0 + +# Running +QEMU_BASE_MACHINE=3D-M virt -cpu max -display none +QEMU_OPTS+=3D$(QEMU_BASE_MACHINE) -semihosting-config enable=3Don,target= =3Dnative,chardev=3Doutput -kernel + +# Simple Record/Replay Test +.PHONY: memory-record +run-memory-record: memory-record memory + $(call run-test, $<, \ + $(QEMU) -monitor none -display none \ + -chardev file$(COMMA)path=3D$<.out$(COMMA)id=3Doutput \ + -icount shift=3D5$(COMMA)rr=3Drecord$(COMMA)rrfile=3Drecord.bin \ + $(QEMU_OPTS) memory) + +.PHONY: memory-replay +run-memory-replay: memory-replay run-memory-record + $(call run-test, $<, \ + $(QEMU) -monitor none -display none \ + -chardev file$(COMMA)path=3D$<.out$(COMMA)id=3Doutput \ + -icount shift=3D5$(COMMA)rr=3Dreplay$(COMMA)rrfile=3Drecord.bin \ + $(QEMU_OPTS) memory) + +EXTRA_RUNS+=3Drun-memory-replay =20 -# We don't currently support the multiarch system tests -undefine MULTIARCH_TESTS +TESTS +=3D $(ARM_TESTS) $(MULTIARCH_TESTS) +EXTRA_RUNS+=3D$(MULTIARCH_RUNS) diff --git a/tests/tcg/arm/system/boot.S b/tests/tcg/arm/system/boot.S new file mode 100644 index 0000000000..7915502ae4 --- /dev/null +++ b/tests/tcg/arm/system/boot.S @@ -0,0 +1,301 @@ +/* + * Minimal ArmV7 system boot code. + * + * Using semihosting for serial output and exit functions. + */ + +/* + * Semihosting interface on ARM AArch32 + * R0 - semihosting call number + * R1 - semihosting parameter + */ +#define semihosting_call svc 0x123456 +#define SYS_WRITEC 0x03 /* character to debug channel */ +#define SYS_WRITE0 0x04 /* string to debug channel */ +#define SYS_EXIT 0x18 + +#define ADP_Stopped_ApplicationExit 0x20026 +#define ADP_Stopped_InternalError 0x20024 + +/* + * Helper macro for the linker calling subroutines from the C code. + */ +.macro endf name + .global \name + .type \name, %function + .size \name, . - \name +.endm + + .section .interrupt_vector, "ax" + .align 5 + +vector_table: + b reset /* reset vector */ + b undef_instr /* undefined instruction vector */ + b software_intr /* software interrupt vector */ + b prefetch_abort /* prefetch abort vector */ + b data_abort /* data abort vector */ + nop /* reserved */ + b IRQ_handler /* IRQ vector */ + b FIQ_handler /* FIQ vector */ + + .text +__start: + ldr r0, =3Dvector_table + mcr p15, 0, r0, c12, c0, 0 /* Set up VBAR */ + + ldr sp, =3Dstack_end /* Set up the stack */ + bl mmu_setup /* Set up the MMU */ + bl main /* Jump to main */ + +endf __start + +_exit: + cmp r0, #0 + ite EQ // if-then-else. "EQ" is for if equal, else otherwise + ldreq r1, =3DADP_Stopped_ApplicationExit // if r0 =3D=3D 0 + ldrne r1, =3DADP_Stopped_InternalError // else + mov r0, #SYS_EXIT + semihosting_call + +endf _exit + + /* + * Helper Functions + */ + +mmu_setup: + /* + * The MMU setup for this is very simple using two stage one + * translations. The first 1Mb section points to the text + * section and the second points to the data and rss. + * Currently the fattest test only needs ~50k for that so we + * have plenty of space. + * + * The short descriptor Section format is as follows: + * + * PA[31:20] - Section Base Address + * NS[19] - Non-secure bit + * 0[18] - Section (1 for Super Section) + * nG[17] - Not global bit + * S[16] - Shareable + * TEX[14:12] - Memory Region Attributes + * AP[15, 11:10] - Access Permission Bits + * IMPDEF[9] + * Domain[8:5] + * XN[4] - Execute never bit + * C[3] - Memory Region Attributes + * B[2] - Memory Region Attributes + * 1[1] + * PXN[0] - Privileged Execute Never + * + * r0 - point at the table + * r1 - address + * r2 - entry + * r3 - common section bits + * r4 - scratch + */ + + /* + * Memory Region Bits + * + * TEX[14:12] =3D 000 + * C[3] =3D 1 + * B[2] =3D 1 + * + * Outer and Inner WB, no write allocate + */ + mov r3, #0 + ldr r4, =3D(3 << 2) + orr r3, r4, r4 + + /* Section bit */ + orr r3, r3, #2 + + /* Page table setup (identity mapping). */ + ldr r0, =3Dttb + + /* First block: .text/RO/execute enabled */ + ldr r1, =3D.text + ldr r2, =3D0xFFF00000 /* 1MB block alignment */ + and r2, r1, r2 + orr r2, r2, r3 /* common bits */ + orr r2, r2, #(1 << 15) /* AP[2] =3D 1 */ + orr r2, r2, #(1 << 10) /* AP[0] =3D 1 =3D> RO @ PL1 */ + + lsr r4, r2, #(20 - 2) + str r2, [r0, r4, lsl #0] /* write entry */ + + /* Second block: .data/RW/no execute */ + ldr r1, =3D.data + ldr r2, =3D0xFFF00000 /* 1MB block alignment */ + and r2, r1, r2 + orr r2, r2, r3 /* common bits */ + orr r2, r2, #(1 << 10) /* AP[0] =3D 1 =3D> RW @ PL1 */ + orr r2, r2, #(1 << 4) /* XN[4] =3D> no execute */ + + lsr r4, r2, #(20 - 2) + str r2, [r0, r4, lsl #0] /* write entry */ + + /* + * DACR - Domain Control + * + * Enable client mode for domain 0 (we don't use any others) + */ + ldr r0, =3D0x1 + mcr p15, 0, r0, c3, c0, 0 + + /* + * TTCBR - Translation Table Base Control Register + * + * EAE[31] =3D 0, 32-bit translation, short descriptor format + * N[2:0] =3D 5 ( TTBRO uses 31:14-5 =3D> 9 bit lookup stage ) + */ + ldr r0, =3D0x5 + mcr p15, 0, r0, c1, c0, 2 + + /* + * TTBR0 -Translation Table Base Register 0 + * + * [31:9] =3D Base address of table + * + * QEMU doesn't really care about the cache sharing + * attributes so we don't need to either. + */ + ldr r0, =3Dttb + mcr p15, 0, r0, c2, c0, 0 + + /* + * SCTLR- System Control Register + * + * TE[30] =3D 0, exceptions to A32 state + * AFE[29] =3D 0, AP[0] is the access permissions bit + * EE[25] =3D 0, Little-endian + * WXN[19] =3D 0 =3D no effect, Write does not imply XN (execute never) + * I[12] =3D Instruction cachability control + * C[2] =3D Data cachability control + * M[0] =3D 1, enable stage 1 address translation for EL0/1 + * + * At this point virtual memory is enabled. + */ + ldr r0, =3D0x1005 + mcr p15, 0, r0, c1, c0, 0 + + isb + + mov pc, lr /* done, return to caller */ + +/* Output a single character to serial port */ +__sys_outc: + STMFD sp!, {r0-r1} // push r0, r1 onto stack + mov r1, sp + mov r0, #SYS_WRITEC + semihosting_call + LDMFD sp!, {r0-r1} // pop r0, r1 from stack + bx lr + +endf __sys_outc + +reset: + ldr r1, =3Dreset_error + b exception_handler + +undef_instr: + ldr r1, =3Dundef_intr_error + b exception_handler + +software_intr: + ldr r1, =3Dsoftware_intr_error + b exception_handler + +prefetch_abort: + ldr r1, =3Dprefetch_abort_error + b exception_handler + +data_abort: + ldr r1, =3Ddata_abort_error + b exception_handler + +IRQ_handler: + ldr r1, =3Dirq_error + b exception_handler + +FIQ_handler: + ldr r1, =3Dfiq_error + b exception_handler + +/* + * Initiate a exit semihosting call whenever there is any exception + * r1 already holds the string. + */ +exception_handler: + mov r0, #SYS_WRITE0 + semihosting_call + mov r0, #SYS_EXIT + mov r1, #1 + semihosting_call + +endf exception_handler + +/* + * We implement a stub raise() function which errors out as tests + * shouldn't trigger maths errors. + */ + .global raise +raise: + mov r0, #SYS_WRITE0 + ldr r1, =3Dmaths_error + semihosting_call + mov r0, #SYS_EXIT + ldr r1, =3DADP_Stopped_InternalError + semihosting_call + +endf raise + + .data + +.data + +reset_error: + .ascii "Reset exception occurred.\n\0" + +undef_intr_error: + .ascii "Undefined Instruction Exception Occurred.\n\0" + +software_intr_error: + .ascii "Software Interrupt Occurred.\n\0" + +prefetch_abort_error: + .ascii "Prefetch Abort Occurred.\n\0" + +data_abort_error: + .ascii "Data Abort Occurred.\n\0" + +irq_error: + .ascii "IRQ exception occurred.\n\0" + +fiq_error: + .ascii "FIQ exception occurred.\n\0" + +maths_error: + .ascii "Software maths exception.\n\0" + + + /* + * 1st Stage Translation table + * 4096 entries, indexed by [31:20] + * each entry covers 1Mb of address space + * aligned on 16kb + */ + .align 15 +ttb: + .space (4096 * 4), 0 + + .align 12 + + /* Space for stack */ + .align 5 + .section .bss +stack: + .space 65536, 0 +stack_end: diff --git a/tests/tcg/arm/system/kernel.ld b/tests/tcg/arm/system/kernel.ld new file mode 100644 index 0000000000..7b3a76dcbf --- /dev/null +++ b/tests/tcg/arm/system/kernel.ld @@ -0,0 +1,24 @@ +ENTRY(__start) + +SECTIONS +{ + /* virt machine, RAM starts at 1gb */ + . =3D (1 << 30); + .text : { + *(.text) + } + .rodata : { + *(.rodata) + } + /* align r/w section to next 2mb */ + . =3D ALIGN(1 << 21); + .data : { + *(.data) + } + .bss : { + *(.bss) + } + /DISCARD/ : { + *(.ARM.attributes) + } +} --=20 2.39.2 _______________________________________________ Devel mailing list -- devel@lists.libvirt.org To unsubscribe send an email to devel-leave@lists.libvirt.org