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Sun, 19 Nov 2023 19:28:26 -0500 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-335-rebdYtjzMGeUx6JSz-WLuA-1; Sun, 19 Nov 2023 19:28:16 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6ECB88007B3; Mon, 20 Nov 2023 00:28:15 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2F3E240C6EB9; Mon, 20 Nov 2023 00:28:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440104; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Lu8QJO9KDwDOmzdkBAnOVeCD39qe2P6zlwVvhT3kRpk=; b=KIf+EneEgcyFvMPVnQ5Eics750BGXTtvXJIywHQlN3SHau6ux1zywLYy1rS+fryGOzQOMA yEOfnLEhTO19ZC9yvwKP125mCGeuyIZFNAVKX27Oaw/LSeSZ88Bw2UYdOj/SFiFz8G0Y9i lgAwrxeqhfIB5Neh9h+zJ3RU8a0RZXY= X-MC-Unique: rebdYtjzMGeUx6JSz-WLuA-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 1/8] machine: Use error handling when CPU type is checked Date: Mon, 20 Nov 2023 10:27:17 +1000 Message-ID: <20231120002724.986326-2-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440162868100001 Content-Type: text/plain; charset="utf-8" QEMU will be terminated if the specified CPU type isn't supported in machine_run_board_init(). The list of supported CPU type names is tracked by mc->valid_cpu_types. The error handling can be used to propagate error messages, to be consistent how the errors are handled for other situations in the same function. No functional change intended. Suggested-by: Igor Mammedov Signed-off-by: Gavin Shan --- hw/core/machine.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 0c17398141..5b45dbbbd5 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1394,6 +1394,7 @@ void machine_run_board_init(MachineState *machine, co= nst char *mem_path, Error * MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); ObjectClass *oc =3D object_class_by_name(machine->cpu_type); CPUClass *cc; + Error *local_err =3D NULL; =20 /* This checkpoint is required by replay to separate prior clock reading from the other reads, because timer polling functions query @@ -1466,15 +1467,16 @@ void machine_run_board_init(MachineState *machine, = const char *mem_path, Error * =20 if (!machine_class->valid_cpu_types[i]) { /* The user specified CPU is not valid */ - error_report("Invalid CPU type: %s", machine->cpu_type); - error_printf("The valid types are: %s", - machine_class->valid_cpu_types[0]); + error_setg(&local_err, "Invalid CPU type: %s", machine->cpu_ty= pe); + error_append_hint(&local_err, "The valid types are: %s", + machine_class->valid_cpu_types[0]); for (i =3D 1; machine_class->valid_cpu_types[i]; i++) { - error_printf(", %s", machine_class->valid_cpu_types[i]); + error_append_hint(&local_err, ", %s", + machine_class->valid_cpu_types[i]); } - error_printf("\n"); + error_append_hint(&local_err, "\n"); =20 - exit(1); + error_propagate(errp, local_err); } } =20 --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1700440160; cv=none; d=zohomail.com; s=zohoarc; b=T6E7l8B0zGkeQUzlinatkdFh8IjxA6YjD8z0u7gYd5CPANqDmNpVwh9YdprSbsTXQhn7X15wow4LDzTwEmXQuN2FicBppMq1kyDIJnqai6V0btMRPFvXno8FwDjBMv5jMemv+1TziKfPxUSX/uIVsj9hVfZjFJbjET6zifYV1Tk= ARC-Message-Signature: i=1; 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Mon, 20 Nov 2023 00:28:23 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E75EC40C6EB9; Mon, 20 Nov 2023 00:28:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440109; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UxakRTy3gKLVb7rdpCW1DoGIz3YW8eabCrYNAMZunnI=; b=QwhGYudDRSYDuTkiM9JwCXlBn0DSBc2sYkqnZ/1/FO09dkrqo0QUweAhU6lrkkTfZ3AeVH hdbILb1GiIyFdFqD+2BtMVSdia91pHk7fSqJys52jknrjFw9gK17wiroC6dCYZAjBD8vns yhjUpnIiXYW2YTF5uYL/wEPbO5srVTs= X-MC-Unique: kjIk2BgMNTeyegkSr5VBug-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 2/8] machine: Introduce helper is_cpu_type_supported() Date: Mon, 20 Nov 2023 10:27:18 +1000 Message-ID: <20231120002724.986326-3-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The logic, to check if the specified CPU type is supported in machine_run_board_init(), is independent enough. Factor it out into helper is_cpu_type_supported(). machine_run_board_init() looks a bit clean with this. Since we're here, @machine_class is renamed to @mc to avoid multiple line spanning of code. The error messages and comments are tweaked a bit either. No functional change intended. Signed-off-by: Gavin Shan --- v6: 'const MachineState *' in is_cpu_type_supported() (Phil) Clearer hint if only one valid CPU is supported (Phil) --- hw/core/machine.c | 88 +++++++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 5b45dbbbd5..d19aec11a3 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1387,13 +1387,57 @@ out: return r; } =20 +static void is_cpu_type_supported(const MachineState *machine, Error **err= p) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + ObjectClass *oc =3D object_class_by_name(machine->cpu_type); + CPUClass *cc; + int i; + + /* + * Check if the user specified CPU type is supported when the valid + * CPU types have been determined. Note that the user specified CPU + * type is provided through '-cpu' option. + */ + if (mc->valid_cpu_types && machine->cpu_type) { + for (i =3D 0; mc->valid_cpu_types[i]; i++) { + if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { + break; + } + } + + /* The user specified CPU type isn't valid */ + if (!mc->valid_cpu_types[i]) { + error_setg(errp, "Invalid CPU type: %s", machine->cpu_type); + if (!mc->valid_cpu_types[1]) { + error_append_hint(errp, "The only valid type is: %s", + mc->valid_cpu_types[0]); + } else { + error_append_hint(errp, "The valid types are: %s", + mc->valid_cpu_types[0]); + } + + for (i =3D 1; mc->valid_cpu_types[i]; i++) { + error_append_hint(errp, ", %s", mc->valid_cpu_types[i]); + } + + error_append_hint(errp, "\n"); + return; + } + } + + /* Check if CPU type is deprecated and warn if so */ + cc =3D CPU_CLASS(oc); + if (cc && cc->deprecation_note) { + warn_report("CPU model %s is deprecated -- %s", + machine->cpu_type, cc->deprecation_note); + } +} =20 void machine_run_board_init(MachineState *machine, const char *mem_path, E= rror **errp) { ERRP_GUARD(); MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); - ObjectClass *oc =3D object_class_by_name(machine->cpu_type); - CPUClass *cc; Error *local_err =3D NULL; =20 /* This checkpoint is required by replay to separate prior clock @@ -1449,42 +1493,10 @@ void machine_run_board_init(MachineState *machine, = const char *mem_path, Error * machine->ram =3D machine_consume_memdev(machine, machine->memdev); } =20 - /* If the machine supports the valid_cpu_types check and the user - * specified a CPU with -cpu check here that the user CPU is supported. - */ - if (machine_class->valid_cpu_types && machine->cpu_type) { - int i; - - for (i =3D 0; machine_class->valid_cpu_types[i]; i++) { - if (object_class_dynamic_cast(oc, - machine_class->valid_cpu_types[i= ])) { - /* The user specified CPU is in the valid field, we are - * good to go. - */ - break; - } - } - - if (!machine_class->valid_cpu_types[i]) { - /* The user specified CPU is not valid */ - error_setg(&local_err, "Invalid CPU type: %s", machine->cpu_ty= pe); - error_append_hint(&local_err, "The valid types are: %s", - machine_class->valid_cpu_types[0]); - for (i =3D 1; machine_class->valid_cpu_types[i]; i++) { - error_append_hint(&local_err, ", %s", - machine_class->valid_cpu_types[i]); - } - error_append_hint(&local_err, "\n"); - - error_propagate(errp, local_err); - } - } - - /* Check if CPU type is deprecated and warn if so */ - cc =3D CPU_CLASS(oc); - if (cc && cc->deprecation_note) { - warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, - cc->deprecation_note); + /* Check if the CPU type is supported */ + is_cpu_type_supported(machine, &local_err); + if (local_err) { + error_propagate(errp, local_err); } =20 if (machine->cgs) { --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Sun, 19 Nov 2023 19:28:32 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 109791C0690B; Mon, 20 Nov 2023 00:28:31 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8DAFD40C6EB9; Mon, 20 Nov 2023 00:28:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440117; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tRTz2OXY+BteRtjoKj83yO+c/KbuK6vMpHN9lwbaC6I=; b=NNeiSBCCcl5VpaUJnjfFTZ5oo4m9EawBikHdL5u4Cgy7xXgTN2LWhndFuThdcAmleL4k6O ZAU/cD8pqoz8OlnlO5KG2IVQo9KTOp/aISK5qd67IfA8T0Ri3xc09VZLHrezc96gZXWZfJ uVQVmV8XgW54dEW2coix5Nl0aWT2ywc= X-MC-Unique: zomvGOJ6O-WhZ08FRBmG2g-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 3/8] machine: Print CPU model name instead of CPU type Date: Mon, 20 Nov 2023 10:27:19 +1000 Message-ID: <20231120002724.986326-4-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440272642100001 Content-Type: text/plain; charset="utf-8" The names of supported CPU models instead of CPU types should be printed when the user specified CPU type isn't supported, to be consistent with the output from '-cpu ?'. Correct the error messages to print CPU model names instead of CPU type names. Signed-off-by: Gavin Shan --- hw/core/machine.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index d19aec11a3..2cdebcffaf 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1392,6 +1392,7 @@ static void is_cpu_type_supported(const MachineState = *machine, Error **errp) MachineClass *mc =3D MACHINE_GET_CLASS(machine); ObjectClass *oc =3D object_class_by_name(machine->cpu_type); CPUClass *cc; + char *model; int i; =20 /* @@ -1408,17 +1409,25 @@ static void is_cpu_type_supported(const MachineStat= e *machine, Error **errp) =20 /* The user specified CPU type isn't valid */ if (!mc->valid_cpu_types[i]) { - error_setg(errp, "Invalid CPU type: %s", machine->cpu_type); + model =3D cpu_model_from_type(machine->cpu_type); + g_assert(model !=3D NULL); + error_setg(errp, "Invalid CPU type: %s", model); + g_free(model); + + model =3D cpu_model_from_type(mc->valid_cpu_types[0]); + g_assert(model !=3D NULL); if (!mc->valid_cpu_types[1]) { - error_append_hint(errp, "The only valid type is: %s", - mc->valid_cpu_types[0]); + error_append_hint(errp, "The only valid type is: %s", mode= l); } else { - error_append_hint(errp, "The valid types are: %s", - mc->valid_cpu_types[0]); + error_append_hint(errp, "The valid types are: %s", model); } + g_free(model); =20 for (i =3D 1; mc->valid_cpu_types[i]; i++) { - error_append_hint(errp, ", %s", mc->valid_cpu_types[i]); + model =3D cpu_model_from_type(mc->valid_cpu_types[i]); + g_assert(model !=3D NULL); + error_append_hint(errp, ", %s", model); + g_free(model); } =20 error_append_hint(errp, "\n"); --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1700440228; cv=none; d=zohomail.com; s=zohoarc; b=msChDeLYY+t72GUH2yoZ4y6grojhcN/gZzKg6Rn96aRdPFuZX7NbHf8AQY2UjWovUYRGXv9I4k1LfC8RFQV7wqbV5UzmiFvGEntbeTQtvQu8F0ZF7Sx+Xr2EIrAOFcoXWWXxzAzCXMp89vzY1kvJHPTj0KXT9cKR7dIHD0/gMlw= ARC-Message-Signature: i=1; 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Mon, 20 Nov 2023 00:28:39 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 89CE540C6EB9; Mon, 20 Nov 2023 00:28:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440124; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0Qk6/QajLgnGyyzUHhMPIDBeq8Pe5C9hI3Ifb+WIAuI=; b=S5ogDMnJUbCXupPSn9dBYKvFJKUtO4LyiS0wx4Y+koAJ0mZwxIN9gK3nqLDaZoaiNrkyix hGO0b+MMYj+fTNZjhy5Z5YTDNN7Ro4jL2qLAcbBw6uAZQdh5W0nUPL+79Jbav9H0pnvCed J/VByZZJ9juBps71KeFZ9PGfuO38xaM= X-MC-Unique: AftiCdGgOAWGqHEpeCoQIg-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 4/8] hw/arm/virt: Hide host CPU model for tcg Date: Mon, 20 Nov 2023 10:27:20 +1000 Message-ID: <20231120002724.986326-5-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440228574100001 Content-Type: text/plain; charset="utf-8" The 'host' CPU model isn't available until KVM or HVF is enabled. For example, the following error messages are seen when the guest is started with option '-cpu cortex-a8' on tcg after the next commit is applied to check the CPU type in machine_run_board_init(). ERROR:../hw/core/machine.c:1423:is_cpu_type_supported: \ assertion failed: (model !=3D NULL) Bail out! ERROR:../hw/core/machine.c:1423:is_cpu_type_supported: \ assertion failed: (model !=3D NULL) Aborted (core dumped) Hide 'host' CPU model until KVM or HVF is enabled. With this applied, the valid CPU models can be shown. qemu-system-aarch64: Invalid CPU type: cortex-a8 The valid types are: cortex-a7, cortex-a15, cortex-a35, \ cortex-a55, cortex-a72, cortex-a76, cortex-a710, a64fx, \ neoverse-n1, neoverse-v1, neoverse-n2, cortex-a53, \ cortex-a57, max Signed-off-by: Gavin Shan Reviewed-by: Richard Henderson --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index be2856c018..668c0d3194 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -220,7 +220,9 @@ static const char *valid_cpus[] =3D { #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) ARM_CPU_TYPE_NAME("host"), +#endif ARM_CPU_TYPE_NAME("max"), }; =20 --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 19 Nov 2023 19:28:48 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1D6C6185A797; Mon, 20 Nov 2023 00:28:47 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 95A5B40C6EB9; Mon, 20 Nov 2023 00:28:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440131; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yMxLzo5Dk1Vn/s3l6DJ5ta6DNvy5+Zb0FdxR9YcyjbE=; b=IJ7TxHIzSMRTWFeXh20yUuohMAKfyKw+BcfDgNug0uakB6kQHqZz/pnt6k5Vkm1CiDZ+MD wMoO3Wb7APq6mYAW8BKNSXpgYMJGjrd3nRT9g3ZWSf7w59EQopiJCEI74dDZeJjuoKZXxG aWxgKXE5Jg8iqrY4LxnjJgpIgEKNDeE= X-MC-Unique: -RN0IpfTOY-_oiBRG5VH7w-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 5/8] hw/arm/virt: Check CPU type in machine_run_board_init() Date: Mon, 20 Nov 2023 10:27:21 +1000 Message-ID: <20231120002724.986326-6-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440176256100003 Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v6: Move valid_cpu_types[] to virt_machine_class_init() (Phil) --- hw/arm/virt.c | 62 +++++++++++++++++++-------------------------------- 1 file changed, 23 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 668c0d3194..04f9f5fa56 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,40 +204,6 @@ static const int a15irqmap[] =3D { [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; =20 -static const char *valid_cpus[] =3D { -#ifdef CONFIG_TCG - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), - ARM_CPU_TYPE_NAME("cortex-a35"), - ARM_CPU_TYPE_NAME("cortex-a55"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("cortex-a76"), - ARM_CPU_TYPE_NAME("cortex-a710"), - ARM_CPU_TYPE_NAME("a64fx"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), -#endif - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - ARM_CPU_TYPE_NAME("host"), -#endif - ARM_CPU_TYPE_NAME("max"), -}; - -static bool cpu_type_valid(const char *cpu) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(valid_cpus); i++) { - if (strcmp(cpu, valid_cpus[i]) =3D=3D 0) { - return true; - } - } - return false; -} - static void create_randomness(MachineState *ms, const char *node) { struct { @@ -2041,11 +2007,6 @@ static void machvirt_init(MachineState *machine) unsigned int smp_cpus =3D machine->smp.cpus; unsigned int max_cpus =3D machine->smp.max_cpus; =20 - if (!cpu_type_valid(machine->cpu_type)) { - error_report("mach-virt: CPU type %s not supported", machine->cpu_= type); - exit(1); - } - possible_cpus =3D mc->possible_cpu_arch_ids(machine); =20 /* @@ -2939,6 +2900,28 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(oc); + static const char * const valid_cpu_types[] =3D { +#ifdef CONFIG_TCG + ARM_CPU_TYPE_NAME("cortex-a7"), + ARM_CPU_TYPE_NAME("cortex-a15"), + ARM_CPU_TYPE_NAME("cortex-a35"), + ARM_CPU_TYPE_NAME("cortex-a55"), + ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("cortex-a710"), + ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), +#endif + ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a57"), +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + ARM_CPU_TYPE_NAME("host"), +#endif + ARM_CPU_TYPE_NAME("max"), + NULL + }; =20 mc->init =3D machvirt_init; /* Start with max_cpus set to 512, which is the maximum supported by K= VM. @@ -2965,6 +2948,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) #else mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("max"); #endif + mc->valid_cpu_types =3D valid_cpu_types; mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; assert(!mc->get_hotplug_handler); --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1700440211; cv=none; d=zohomail.com; s=zohoarc; b=NfmgsosWPzVGDuzHiOqYZ3s8ck2D5KbF6nUD2n+MNaXkXFRe/5D5Yq9YqSrGEG82K1MQ8e9P3ym2+l/i2hkICn2AvYuqxOwSZtSyfIga10h6sKdKjX7VzFRfWcy1aKRKI1LTDoGEE35DOA8Wav6qXiPVleRxfbPdFzf0crXxr0A= ARC-Message-Signature: i=1; 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Mon, 20 Nov 2023 00:28:54 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9787040C6EB9; Mon, 20 Nov 2023 00:28:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440140; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KF224YbC74LCUQQq9+6bTYrLJvVT9u5roGpclmEXhS8=; b=fvLGgAOv2QhK5gtW+gA1BnQ9WD1psiehc7F60arsUCnVjPqH0pRzMviKzbhpnKlhdWNqnk 7XrZwcsOAMtCG1+EUgqXFjXwtz5C1oDB7P8bgaqoxAeZMzerfqZjyTCMbt5fW9Wf13F/G+ H2qIQohjArEFmqzLPxOquSxfmdwtmG4= X-MC-Unique: Fq7r4K6gN-ySqhhR5BTuwQ-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 6/8] hw/arm/sbsa-ref: Check CPU type in machine_run_board_init() Date: Mon, 20 Nov 2023 10:27:22 +1000 Message-ID: <20231120002724.986326-7-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440212411100007 Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Leif Lindholm Reviewed-by: Richard Henderson --- v6: Move valid_cpu_types[] to sbsa_ref_class_init() (Phil) --- hw/arm/sbsa-ref.c | 36 ++++++++++-------------------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index f3c9704693..477dca0637 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,27 +145,6 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_GWDT_WS0] =3D 16, }; =20 -static const char * const valid_cpus[] =3D { - ARM_CPU_TYPE_NAME("cortex-a57"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("neoverse-n1"), - ARM_CPU_TYPE_NAME("neoverse-v1"), - ARM_CPU_TYPE_NAME("neoverse-n2"), - ARM_CPU_TYPE_NAME("max"), -}; - -static bool cpu_type_valid(const char *cpu) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(valid_cpus); i++) { - if (strcmp(cpu, valid_cpus[i]) =3D=3D 0) { - return true; - } - } - return false; -} - static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; @@ -733,11 +712,6 @@ static void sbsa_ref_init(MachineState *machine) const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; =20 - if (!cpu_type_valid(machine->cpu_type)) { - error_report("sbsa-ref: CPU type %s not supported", machine->cpu_t= ype); - exit(1); - } - if (kvm_enabled()) { error_report("sbsa-ref: KVM is not supported for this machine"); exit(1); @@ -898,10 +872,20 @@ static void sbsa_ref_instance_init(Object *obj) static void sbsa_ref_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), + ARM_CPU_TYPE_NAME("max"), + NULL, + }; =20 mc->init =3D sbsa_ref_init; mc->desc =3D "QEMU 'SBSA Reference' ARM Virtual Machine"; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("neoverse-n1"); + mc->valid_cpu_types =3D valid_cpu_types; mc->max_cpus =3D 512; mc->pci_allow_0_address =3D true; mc->minimum_page_bits =3D 12; --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1700440252; cv=none; d=zohomail.com; s=zohoarc; b=d+8YKx4YTklxvsHSfa0OETjhzWocESsUDO2tisgc00rrQyqAzdz3afcpScQgT0WmZ4noCQrfwkjClaAYEhArWR9jTW1W8XOrIT4o2QtU3F7WcqaddASPbmZ4juM3cSic93J06GH4TqeyJhBSZ5of4G1MqCOeVgAguRCbgvBgHkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700440252; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 20 Nov 2023 00:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440148; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w+qtphYnj/pT3fYoVfsr4aPDYGcbxcq96VDWEstwRy0=; b=Vskps1gVM5fOEUENfM0Yvu558aLJ0YTxRHuoJLXy5Y7RsQkFjCFg49ZEcgdDF8eB04XFhx s+/ew+sCkpveoakqxV64fuRpjGumTYmtMAaF9wzsK0MeO/R6ycMJgCtn1AoxAFZhzMVQQ3 TK+4FTPifuXBLqCeolifCEvB2tBel7k= X-MC-Unique: XeQ_xvmDOYK38NDBX6eVnw-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 7/8] hw/arm: Check CPU type in machine_run_board_init() Date: Mon, 20 Nov 2023 10:27:23 +1000 Message-ID: <20231120002724.986326-8-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440254642100007 Content-Type: text/plain; charset="utf-8" Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Richard Henderson --- v6: To have unified valid_cpu_types[] and move it to board's class_init() function (Phil) --- hw/arm/bananapi_m2u.c | 12 ++++++------ hw/arm/cubieboard.c | 12 ++++++------ hw/arm/mps2-tz.c | 26 ++++++++++++++++++++------ hw/arm/mps2.c | 26 ++++++++++++++++++++------ hw/arm/msf2-som.c | 12 ++++++------ hw/arm/musca.c | 12 +++++------- hw/arm/npcm7xx_boards.c | 12 +++++------- hw/arm/orangepi.c | 12 ++++++------ 8 files changed, 74 insertions(+), 50 deletions(-) diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 8f24b18d8c..0a4b6f29b1 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -71,12 +71,6 @@ static void bpim2u_init(MachineState *machine) exit(1); } =20 - /* Only allow Cortex-A7 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) { - error_report("This board can only be used with cortex-a7 CPU"); - exit(1); - } - r40 =3D AW_R40(object_new(TYPE_AW_R40)); object_property_add_child(OBJECT(machine), "soc", OBJECT(r40)); object_unref(OBJECT(r40)); @@ -133,12 +127,18 @@ static void bpim2u_init(MachineState *machine) =20 static void bpim2u_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; + mc->desc =3D "Bananapi M2U (Cortex-A7)"; mc->init =3D bpim2u_init; mc->min_cpus =3D AW_R40_NUM_CPUS; mc->max_cpus =3D AW_R40_NUM_CPUS; mc->default_cpus =3D AW_R40_NUM_CPUS; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_size =3D 1 * GiB; mc->default_ram_id =3D "bpim2u.ram"; } diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 29146f5018..b976727eef 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -52,12 +52,6 @@ static void cubieboard_init(MachineState *machine) exit(1); } =20 - /* Only allow Cortex-A8 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) !=3D 0) { - error_report("This board can only be used with cortex-a8 CPU"); - exit(1); - } - a10 =3D AW_A10(object_new(TYPE_AW_A10)); object_property_add_child(OBJECT(machine), "soc", OBJECT(a10)); object_unref(OBJECT(a10)); @@ -114,8 +108,14 @@ static void cubieboard_init(MachineState *machine) =20 static void cubieboard_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a8"), + NULL + }; + mc->desc =3D "cubietech cubieboard (Cortex-A8)"; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a8"); + mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_size =3D 1 * GiB; mc->init =3D cubieboard_init; mc->block_default_type =3D IF_IDE; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 668db5ed61..5d8cdc1a4c 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -813,12 +813,6 @@ static void mps2tz_common_init(MachineState *machine) int num_ppcs; int i; =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be %s", sz); @@ -1318,6 +1312,10 @@ static void mps2tz_an505_class_init(ObjectClass *oc,= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN505 FPGA image for Cortex-M33"; mc->default_cpus =3D 1; @@ -1325,6 +1323,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, = void *data) mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN505; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41045050; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->apb_periph_frq =3D mmc->sysclk_frq; @@ -1347,6 +1346,10 @@ static void mps2tz_an521_class_init(ObjectClass *oc,= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; mc->default_cpus =3D 2; @@ -1354,6 +1357,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, = void *data) mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN521; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41045210; mmc->sysclk_frq =3D 20 * 1000 * 1000; /* 20MHz */ mmc->apb_periph_frq =3D mmc->sysclk_frq; @@ -1376,6 +1380,10 @@ static void mps3tz_an524_class_init(ObjectClass *oc,= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; =20 mc->desc =3D "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; mc->default_cpus =3D 2; @@ -1383,6 +1391,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, = void *data) mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN524; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41045240; mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ mmc->apb_periph_frq =3D mmc->sysclk_frq; @@ -1410,6 +1419,10 @@ static void mps3tz_an547_class_init(ObjectClass *oc,= void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m55"), + NULL + }; =20 mc->desc =3D "ARM MPS3 with AN547 FPGA image for Cortex-M55"; mc->default_cpus =3D 1; @@ -1417,6 +1430,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, = void *data) mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN547; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m55"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41055470; mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ mmc->apb_periph_frq =3D 25 * 1000 * 1000; /* 25MHz */ diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 292a180ad2..bd873cc5de 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -142,12 +142,6 @@ static void mps2_common_init(MachineState *machine) QList *oscclk; int i; =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be %s", sz); @@ -484,10 +478,15 @@ static void mps2_an385_class_init(ObjectClass *oc, vo= id *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN385 FPGA image for Cortex-M3"; mmc->fpga_type =3D FPGA_AN385; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41043850; mmc->psram_base =3D 0x21000000; mmc->ethernet_base =3D 0x40200000; @@ -498,10 +497,15 @@ static void mps2_an386_class_init(ObjectClass *oc, vo= id *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN386 FPGA image for Cortex-M4"; mmc->fpga_type =3D FPGA_AN386; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41043860; mmc->psram_base =3D 0x21000000; mmc->ethernet_base =3D 0x40200000; @@ -512,10 +516,15 @@ static void mps2_an500_class_init(ObjectClass *oc, vo= id *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m7"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN500 FPGA image for Cortex-M7"; mmc->fpga_type =3D FPGA_AN500; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m7"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41045000; mmc->psram_base =3D 0x60000000; mmc->ethernet_base =3D 0xa0000000; @@ -526,10 +535,15 @@ static void mps2_an511_class_init(ObjectClass *oc, vo= id *data) { MachineClass *mc =3D MACHINE_CLASS(oc); MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; =20 mc->desc =3D "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3= "; mmc->fpga_type =3D FPGA_AN511; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types =3D valid_cpu_types; mmc->scc_id =3D 0x41045110; mmc->psram_base =3D 0x21000000; mmc->ethernet_base =3D 0x40200000; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 7b3106c790..eb74b23797 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -55,12 +55,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machin= e) MemoryRegion *ddr =3D g_new(MemoryRegion, 1); Clock *m3clk; =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, &error_fatal); memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); @@ -106,9 +100,15 @@ static void emcraft_sf2_s2s010_init(MachineState *mach= ine) =20 static void emcraft_sf2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "SmartFusion2 SOM kit from Emcraft (M2S010)"; mc->init =3D emcraft_sf2_s2s010_init; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 6eeee57c9d..770ec1a15c 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -355,7 +355,6 @@ static void musca_init(MachineState *machine) { MuscaMachineState *mms =3D MUSCA_MACHINE(machine); MuscaMachineClass *mmc =3D MUSCA_MACHINE_GET_CLASS(mms); - MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *ssedev; DeviceState *dev_splitter; @@ -366,12 +365,6 @@ static void musca_init(MachineState *machine) assert(mmc->num_irqs <=3D MUSCA_NUMIRQ_MAX); assert(mmc->num_mpcs <=3D MUSCA_MPC_MAX); =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); mms->s32kclk =3D clock_new(OBJECT(machine), "S32KCLK"); @@ -604,11 +597,16 @@ static void musca_init(MachineState *machine) static void musca_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; =20 mc->default_cpus =3D 2; mc->min_cpus =3D mc->default_cpus; mc->max_cpus =3D mc->default_cpus; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D musca_init; } =20 diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2aef579aac..2999b8b96d 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -121,15 +121,8 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *= machine, uint32_t hw_straps) { NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_GET_CLASS(machine); - MachineClass *mc =3D MACHINE_CLASS(nmc); Object *obj; =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with %s", - mc->default_cpu_type); - exit(1); - } - obj =3D object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", &error_abort, NULL); object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abo= rt); @@ -463,12 +456,17 @@ static void npcm7xx_set_soc_type(NPCM7xxMachineClass = *nmc, const char *type) static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; =20 mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; mc->default_ram_id =3D "ram"; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types =3D valid_cpu_types; } =20 /* diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index f3784d45ca..77e328191d 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -49,12 +49,6 @@ static void orangepi_init(MachineState *machine) exit(1); } =20 - /* Only allow Cortex-A7 for this board */ - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) { - error_report("This board can only be used with cortex-a7 CPU"); - exit(1); - } - h3 =3D AW_H3(object_new(TYPE_AW_H3)); object_property_add_child(OBJECT(machine), "soc", OBJECT(h3)); object_unref(OBJECT(h3)); @@ -111,6 +105,11 @@ static void orangepi_init(MachineState *machine) =20 static void orangepi_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; + mc->desc =3D "Orange Pi PC (Cortex-A7)"; mc->init =3D orangepi_init; mc->block_default_type =3D IF_SD; @@ -119,6 +118,7 @@ static void orangepi_machine_init(MachineClass *mc) mc->max_cpus =3D AW_H3_NUM_CPUS; mc->default_cpus =3D AW_H3_NUM_CPUS; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); + mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_size =3D 1 * GiB; mc->default_ram_id =3D "orangepi.ram"; } --=20 2.41.0 From nobody Wed Nov 27 04:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1700440250; cv=none; d=zohomail.com; s=zohoarc; b=cNt8+HYBvXZDlHHaMnK2fnGjIEkoO8SMrBfwnLftJG0IzLvAYXCvLXe5c5xhLHoPnZ9FCPSfsdL1q6u+8av3x15eKFE0aCEqq2b8cVFkhS+VFr6+khfi7iTnqr8o3nZOJjcEogfhOWyQptH/ol/rTVozz8JqclecxnQguK5Jx14= ARC-Message-Signature: i=1; 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Mon, 20 Nov 2023 00:29:11 +0000 (UTC) Received: from gshan.redhat.com (unknown [10.64.136.87]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5F56B40C6EB9; Mon, 20 Nov 2023 00:29:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1700440156; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w2Opa+n3VWOIBf82pAqFV3jjJGG/p3OT/M7D+mi8Yb8=; b=W7isZnoxeKU+uoEIOKjjfAqP24BuysuSAClj4h40HgiImqrD0qNarRyrgEah+iqIPQX7Jq 1cxV3Wxn1keoqq+fw9RBN544b5yx0nc7j6RRy26YH10MfpM+SJJ0mP4bR3Vyg00VWHE9vF VxAV5OV+tTGacaq8iXba5Q8VLCMvIF8= X-MC-Unique: sQAXnZ_pNNCp-ERVkfESTg-1 From: Gavin Shan To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, imammedo@redhat.com, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, shan.gavin@gmail.com Subject: [PATCH v6 8/8] hw/riscv/shakti_c: Check CPU type in machine_run_board_init() Date: Mon, 20 Nov 2023 10:27:24 +1000 Message-ID: <20231120002724.986326-9-gshan@redhat.com> In-Reply-To: <20231120002724.986326-1-gshan@redhat.com> References: <20231120002724.986326-1-gshan@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1700440250557100001 Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v6: Move valid_cpu_types[] to shakti_c_machine_class_init() (Phil) --- hw/riscv/shakti_c.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 12ea74b032..3888034c2b 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -28,7 +28,6 @@ #include "exec/address-spaces.h" #include "hw/riscv/boot.h" =20 - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -47,12 +46,6 @@ static void shakti_c_machine_state_init(MachineState *ms= tate) ShaktiCMachineState *sms =3D RISCV_SHAKTI_MACHINE(mstate); MemoryRegion *system_memory =3D get_system_memory(); =20 - /* Allow only Shakti C CPU for this platform */ - if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) !=3D 0) { - error_report("This board can only be used with Shakti C CPU"); - exit(1); - } - /* Initialize SoC */ object_initialize_child(OBJECT(mstate), "soc", &sms->soc, TYPE_RISCV_SHAKTI_SOC); @@ -82,9 +75,15 @@ static void shakti_c_machine_instance_init(Object *obj) static void shakti_c_machine_class_init(ObjectClass *klass, void *data) { MachineClass *mc =3D MACHINE_CLASS(klass); + static const char * const valid_cpu_types[] =3D { + RISCV_CPU_TYPE_NAME("shakti-c"), + NULL + }; + mc->desc =3D "RISC-V Board compatible with Shakti SDK"; mc->init =3D shakti_c_machine_state_init; mc->default_cpu_type =3D TYPE_RISCV_CPU_SHAKTI_C; + mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_id =3D "riscv.shakti.c.ram"; } =20 --=20 2.41.0