From nobody Wed Nov 27 07:42:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1700206928; cv=none; d=zohomail.com; s=zohoarc; b=kGRHJx7Nn7KYMcXUYMDPhbM5pyympYAFVycUvD59P2diMXl5tj/BGxxyiwbpIQSd7GSV3woWfPY6vvl4PduQH7JDK9PWseBBwKy+kB7ZFD0EJW0Cyvqmyg8jCBT+4YTOHuldFcegJv+cqPxOttOd1NH2jsRX0agQ8OZwFjYfiV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700206928; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=klqHgOSWt17ZHKXiSBNRUNWrvFYoF9XB0XuG0ce39U4=; b=C0wIx0VKheKY6DQI4fSl1t/7coL7Ma7laDHQtguUnAJQrqsbKxTet7A1DcYs/zEvU/T2YrF2YEn7YdwnCd/+7m4Ia9yyUHef8F26lkwFuHlTALooTtGn8hneXQdkVyFLeW0cZ/F+4S5lZcNhE7QChUIkH2hL08/2aw+Ys2qQvsE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700206928854245.84224661589712; Thu, 16 Nov 2023 23:42:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3tT4-0006YP-Fp; Fri, 17 Nov 2023 02:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3tT0-0006Qa-4h for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:40:42 -0500 Received: from mgamail.intel.com ([134.134.136.65]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3tSu-0008AT-Sa for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:40:41 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 23:40:19 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2023 23:40:15 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700206836; x=1731742836; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5tYS4G2HZatnuAwGoJ1pL4agrEatB27fQNYS9iNFe6o=; b=k6oio156EKcRzb10lKPXsWH3NfzLNe666e/IbsvrFQ3oR4y6CkNi/yO9 bhX7b6PLLgs7ygommjU7FHBUDsDjpTMpQd87LoIxw5q854mYmDH3Pz+vW S5q5WsPyQIUeK+JjNtb0umXMDccmaSTWKi8XzjxygRu9qU3TmbPJc+qmL xFZlKfLwlmTATS/omv6qgXmAqCQvA35E6SNHo+JRJYoezoArL1S33HDWD S6Kg7ef1GhcLogOBc2rGcpocUgAQiv1gqH927wIGf3UyFCQPxyUSkYgiU kl1FY4CCel/st4W/z/yxmfJ2H1rwCSPYT/vHpCvDT27eQJISK9C6UMhjd w==; X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="395180433" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="395180433" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="883042875" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="883042875" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v6 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Fri, 17 Nov 2023 15:51:05 +0800 Message-Id: <20231117075106.432499-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117075106.432499-1-zhao1.liu@linux.intel.com> References: <20231117075106.432499-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.65; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.117, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1700206930538100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId =3D LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the calculation of this field should be same as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of APIC ID to calculate this field. [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Signed-off-by: Zhao Liu Reviewed-by: Babu Moger Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Rewrite the subject. (Babu) * Delete the original "comment/help" expression, as this behavior is confirmed for AMD CPUs. (Babu) * Rename "num_apic_ids" (v3) to "num_sharing_cache" to match spec definition. (Babu) Changes since v1: * Rename "l3_threads" to "num_apic_ids" in encode_cache_cpuid8000001d(). (Yanan) * Add the description of the original commit and add Cc. --- target/i386/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 86445e833a2d..3ddedd6de120 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -483,7 +483,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_sharing_cache; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -492,13 +492,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->modules_per_die * - topo_info->cores_per_module * - topo_info->threads_per_core; - *eax |=3D (l3_threads - 1) << 14; + num_sharing_cache =3D 1 << apicid_die_offset(topo_info); } else { - *eax |=3D ((topo_info->threads_per_core - 1) << 14); + num_sharing_cache =3D 1 << apicid_core_offset(topo_info); } + *eax |=3D (num_sharing_cache - 1) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1