From nobody Wed Nov 27 06:41:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1700206900; cv=none; d=zohomail.com; s=zohoarc; b=Jt/8rCFHQJMzhDgd6cB7VJgQ3CRAyl34KkHo9ltv/WAkFo/cVRvZD9gn0Ka5ZLL8rpfNhbV9xNOWdcYHO6EkD6tvz+MKZzUc04JwDb8eypbIimheb4b8fbVRcJfJb8gGJcUqqHAUXufRC8959rGYKFZRmVXeHqdx0bZJQwRkI28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700206900; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jI5rClrUd8/6DRx6pAt1AVGcuz9COUUl4WOgj0Z0z6s=; b=lckA+fieBpSNhlX4VcqF9mYrA9ZgatDyFcV27yCe051iTFWFn+ZXntwT579ha9mgyrj7p+RhuNnEJRxiRHMKBg1rLWkGt88rSK/EtI3tJDYzoRX4HsO8G5P2EPT5hcQX6TUzuMI0fmF2iCGrCpzPpciPoiPYxKZUX2gmpUZXsro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700206900082914.162811951343; Thu, 16 Nov 2023 23:41:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3tSt-000632-TJ; Fri, 17 Nov 2023 02:40:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3tSo-0005ek-CK for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:40:30 -0500 Received: from mgamail.intel.com ([134.134.136.65]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3tSl-00083O-NH for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:40:30 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2023 23:40:12 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2023 23:40:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700206827; x=1731742827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rEdU6NYjtG2tsuq6aWGcJvGfg3pqbFRsCfqR1q1CBKo=; b=a0rf5RLJyfWWn/Zw2iJDzSrSwpcjNOklPoC/HII721226BgABkDDlXps LSUXcdnCA4ucVAS2rLdLUNwBsBuJ98PS7jU3Hemhza9vKFBuyt/A7wV+Y 4AYaI5+Sdx/NLqanRwVR6V6jvh2aOteKyeouJgWL9wvlvCF7rFf1DMPqx LkVqYE2Y9Xa2hbIdl77ttPLXpAV8yefUMsXmy18WB7wIAzqBXeaQMAwqE POOvFctxTaGZyEwyxtdslX/Cpw9jJNFQseJaxGiQvcG65TeaKW79DsYey KOXoKaSW4zQXeImcQaJfTR8iUEE17dFtcLM1+NHHgJrTkmjS95vhH+Eas w==; X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="395180417" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="395180417" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10896"; a="883042849" X-IronPort-AV: E=Sophos;i="6.04,206,1695711600"; d="scan'208";a="883042849" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Babu Moger , Yongwei Ma , Zhao Liu Subject: [PATCH v6 13/16] i386: Add cache topology info in CPUCacheInfo Date: Fri, 17 Nov 2023 15:51:03 +0800 Message-Id: <20231117075106.432499-14-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117075106.432499-1-zhao1.liu@linux.intel.com> References: <20231117075106.432499-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.65; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.117, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1700206900454100002 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a specific cpu topology, such as the connection between L2 cache and core level, and the connection between L3 cache and die level. In fact, the settings of these topologies depend on the specific platform and are not static. For example, on Alder Lake-P, every four Atom cores share the same L2 cache. Thus, we should explicitly define the corresponding cache topology for different cache models to increase scalability. Except legacy_l2_cache_cpuid2 (its default topo level is CPU_TOPO_LEVEL_UNKNOW), explicitly set the corresponding topology level for all other cache models. In order to be compatible with the existing cache topology, set the CPU_TOPO_LEVEL_CORE level for the i/d cache, set the CPU_TOPO_LEVEL_CORE level for L2 cache, and set the CPU_TOPO_LEVEL_DIE level for L3 cache. The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits 25:14] will be set based on CPUCacheInfo.share_level. Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin --- Changes since v3: * Fix cache topology uninitialization bugs for some AMD CPUs. (Babu) * Move the CPUTopoLevel enumeration definition to the previous 0x1f rework patch. Changes since v1: * Add the prefix "CPU_TOPO_LEVEL_*" for CPU topology level names. (Yanan) * (Revert, pls refer "i386: Decouple CPUID[0x1F] subleaf with specific topology level") Rename the "INVALID" level to CPU_TOPO_LEVEL_UNKNOW. (Yanan) --- target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 7 +++++++ 2 files changed, 43 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 84f305130a6f..5dcc41329805 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -558,6 +558,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -572,6 +573,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -585,6 +587,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -599,6 +602,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -612,6 +616,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -621,6 +626,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { .size =3D 2 * MiB, .line_size =3D 64, .associativity =3D 8, + .share_level =3D CPU_TOPO_LEVEL_INVALID, }; =20 =20 @@ -634,6 +640,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -649,6 +656,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -1947,6 +1955,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1959,6 +1968,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1969,6 +1979,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1982,6 +1993,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -1997,6 +2009,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2009,6 +2022,7 @@ static CPUCaches epyc_v4_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2019,6 +2033,7 @@ static CPUCaches epyc_v4_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2032,6 +2047,7 @@ static CPUCaches epyc_v4_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2047,6 +2063,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2059,6 +2076,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2069,6 +2087,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2082,6 +2101,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2097,6 +2117,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2109,6 +2130,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2119,6 +2141,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2132,6 +2155,7 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2147,6 +2171,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2159,6 +2184,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2169,6 +2195,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2182,6 +2209,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2197,6 +2225,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2209,6 +2238,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2219,6 +2249,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2232,6 +2263,7 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2247,6 +2279,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2259,6 +2292,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2269,6 +2303,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .partitions =3D 1, .sets =3D 2048, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2282,6 +2317,7 @@ static const CPUCaches epyc_genoa_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D false, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6a6356e34e62..dafc4b4a92f2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1597,6 +1597,13 @@ typedef struct CPUCacheInfo { * address bits. CPUID[4].EDX[bit 2]. */ bool complex_indexing; + + /* + * Cache Topology. The level that cache is shared in. + * Used to encode CPUID[4].EAX[bits 25:14] or + * CPUID[0x8000001D].EAX[bits 25:14]. + */ + enum CPUTopoLevel share_level; } CPUCacheInfo; =20 =20 --=20 2.34.1