From nobody Wed Nov 27 07:55:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700205524; cv=none; d=zohomail.com; s=zohoarc; b=NOIaoePhySqzBT1Dn5aNc36X8HXDfoYCpdyTQijejPNacPZ8GqxceyZHcMT5Ury/IIjQiksVlOkZh5+ziH7Afw4toHVqSH/AZnKTewsyoXb2IWTtWgcLhmzSCuUkY9BBEq6QxVUwFSXkCPgvIriNl8Vq4v+2n6EPIERVyUCCmis= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700205524; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jkPUT0M619zXl9UJEyr5oJWxqcVgknV+BijjQqGI0PI=; b=le3xaH08Tt78ExLl1+kvUt8O3oBFO3Ml+tMj4dKaJQRYAD9MbOh+Ia8kbXUytdhS2fGZlzx70v81BmM1oX4zcMjixMisVptoH0ymhHjmKLeY+IhdSgtKQMzTa73SsEAvJKVhDhWw6RXANxUFReSXpPkYwYZOe+dO0tvI6ci2JKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700205524523283.26854138504063; Thu, 16 Nov 2023 23:18:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3t6h-0005Sp-3S; Fri, 17 Nov 2023 02:17:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3t6e-0005RY-P9 for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:17:36 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r3t6c-0004Kj-86 for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:17:35 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-32f87b1c725so1217732f8f.3 for ; Thu, 16 Nov 2023 23:17:33 -0800 (PST) Received: from m1x-phil.lan (bd137-h02-176-184-46-187.dsl.sta.abo.bbox.fr. [176.184.46.187]) by smtp.gmail.com with ESMTPSA id q16-20020adfcd90000000b0032d9caeab0fsm1409272wrj.77.2023.11.16.23.17.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Nov 2023 23:17:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700205452; x=1700810252; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jkPUT0M619zXl9UJEyr5oJWxqcVgknV+BijjQqGI0PI=; b=nlT6RRn1osVMNVwVIYTzC8UV4L+/I+iRb52SLisKanQB6HUTLQ+Ab8oM6mJCPAipkR 6O6F91rqsiCTqSy9ob8yRmaCKxRn0HBs/qyo+PWUxaum7hoh6YLnnHdsxcnKfyc0+zhS LrNVVH7P//5Y0OXNVKCgpSno6sOAzfhVVtcGzbEC9cz4ix2yEr9Tppnb2ecYrQLgcbmt U28a6aVAJttO29uYhk2lxXPLH1DmgwjwUhpj2aZ0RJuxbDZEwdBeOkAocKF0BF+fiQ1t dXfdUsnKP2tiisq4GsoLOK36gTvXXBxet1kKavkeqRQoaE/VToW0Mssaaj/5MCsoMfv7 lE4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700205452; x=1700810252; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jkPUT0M619zXl9UJEyr5oJWxqcVgknV+BijjQqGI0PI=; b=wjpIwgNYa0zAtOSCECstaJtRurz5kEhEhAYq/REucx+ynv4eV0hRwLvoeqPdZzxElg yBAkYhU5I4miTKhEFnnpBwMfO8Sp6aTLUlPbfsyjsCOQf6Wmk4LuozG9qtqDxlhLuijw SsGiYQh/W82PdaRdPsNlI9F5zHIdGXkviSjMltdEMMZF6igU3PLLSBqEoeueU/9tqtyH EhfYnUMSaMbPxcGQg/dyQZfDfoOd8OQOlGh2SzWGEqo79XVwWqBpvSKY+OudIprb1fH6 lXR4jy+ALi67K2itXevfTZO5NWqeVVzJNJ3krrxUe7pBMDsCDH2UO5iELirSX+/7mge4 JpLA== X-Gm-Message-State: AOJu0Yzaf7McA/zPZsJ6tNdhMCeADfMoNmx9toKRfJKijRb4dGLnN8tb u0W3K6O1yIHjNCJJ+9uK2lNNqMULnDDWVlF0W30= X-Google-Smtp-Source: AGHT+IHFTvcbCgKP7OFB5B5FhkYKXGMpXDSZe+jYZyBLuao/KsF0vglURAPe6cpUVno6sFuauNdYvg== X-Received: by 2002:adf:ed41:0:b0:32d:b9c5:82fc with SMTP id u1-20020adfed41000000b0032db9c582fcmr11874479wro.36.1700205452492; Thu, 16 Nov 2023 23:17:32 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Subbaraya Sundeep , Arnaud Minier , Igor Mammedov , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Tyrone Ting , Hao Wu , Marcel Apfelbaum , Felipe Balbi , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Alistair Francis , Yanan Wang , Richard Henderson , Eduardo Habkost , Peter Maydell , Helge Deller , Subbaraya Sundeep , Alexandre Iooss , Gavin Shan Subject: [PATCH-for-8.2? v2 4/4] hw/arm/stm32f100: Report error when incorrect CPU is used Date: Fri, 17 Nov 2023 08:17:04 +0100 Message-ID: <20231117071704.35040-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231117071704.35040-1-philmd@linaro.org> References: <20231117071704.35040-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700205526655100003 The 'stm32vldiscovery' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b28..a74d7b369c 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) =20 struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; =20 - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9f..b90d440d7a 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } =20 -static Property stm32f100_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f100_soc_info =3D { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952f..190db6118b 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) =20 static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init =3D stm32vldiscovery_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) --=20 2.41.0