From nobody Wed Nov 27 04:52:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700205500; cv=none; d=zohomail.com; s=zohoarc; b=XPpqkQ78798zfndvrBnunwXX5aUjyESgqDr9YfkLNXuBARGNcaP4xUPw06eYU2TAfN5kq+KN3kpBCHzHD0WBTUFi+3ItrW36/+rKmfuLkjJvFbQrQ4AY6E8RnHRScgRwlXUE5fFNJ6HSb1tUjoHcbnyDp7o1PzKL5vNWbwKrjkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700205500; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CHdKGB9IdVR9xVcd4O1PYbu10XnVv29sfGXQ2wqVVus=; b=gIlvptYf2wX/lkHc480eTVrrGsgZdWquBq57Xogly7j4zPjTzcBGER+Gc/U9Ip22cOmUlYzlp63l5zZ/CAg/XUs33E05d3sK+5GZ47GclSMnIqnJQjMmDjwxZzqwXkP3718G2H53zFwNWsOvdhK1xV4Ma0j8ph4Mx3ZYZ5Tul/o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170020550058191.14634824344535; Thu, 16 Nov 2023 23:18:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3t6V-0005Ld-51; Fri, 17 Nov 2023 02:17:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3t6O-0005JT-3q for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:17:20 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r3t6M-0004Gd-CB for qemu-devel@nongnu.org; Fri, 17 Nov 2023 02:17:19 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40839652b97so12751025e9.3 for ; Thu, 16 Nov 2023 23:17:15 -0800 (PST) Received: from m1x-phil.lan (bd137-h02-176-184-46-187.dsl.sta.abo.bbox.fr. [176.184.46.187]) by smtp.gmail.com with ESMTPSA id u3-20020a05600c00c300b0040648217f4fsm5905684wmm.39.2023.11.16.23.17.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Nov 2023 23:17:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700205434; x=1700810234; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CHdKGB9IdVR9xVcd4O1PYbu10XnVv29sfGXQ2wqVVus=; b=e9nVJquOed/Ba0IwNQX3PJV6LcyTUTvHAcMVSpuD6aNC+TYgCF8MbxxyPG4Oa2iAUg 06kZt8uk+BNestrxVb7w14BClgTF28d5G00EIfN48BePlxBqjJvVBSj9wEUfgSeg5sgw modZvWAEJok1h1g7MBvgxT3nUpI9nXgQpZkNUBqMm+ZF266k9LfC2PB6AVsv5UltvvBF FB09qYD/t5pmOhr3eqHDfDsS0V6GwfuYxicMW3l9+ANQ4oIsfDlTtYsi5MAyWK4JVwXl pso+WqVWBEYkneCZ6HAdi33kD77YwO+6fGwflm7QDgCEQDYZdJY5a6VHQbDEN0W7l8Yn iWlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700205434; x=1700810234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CHdKGB9IdVR9xVcd4O1PYbu10XnVv29sfGXQ2wqVVus=; b=XkRtJ+3mZv3sZaWGZQdpD2/MOdYTl8CFz2uhcb1lLUf5ct6JRr4ZSG1H7xr5Ht13uj Rj1wdVwodAs9JhVT9rPSv76ZTpMeHokvOUx/ywNxe+wwQoodqnAdh29K6Nb3jtOoUExt nmyp7XWVBLHa+8pA1riLgSwyiNKbjbNmAqWhA2rO0vUmc0s8jxQRjZiGeJSKXATZ1vev eCjmOmxMeAzTrsMjR24P10L87yC2Imo+E/w7iJSPouovxABfYLA1+91XQVQQIc4+m2nD YMnuOxVPnCI95s7k7QxG7Un+6ojmW9rXKXN7Uk65QfLaesKStLEUkPElwyMybB+hMZxi HM+g== X-Gm-Message-State: AOJu0YxXNakQJXao2L6/L+CH3V9pyjJSIl9kmNnvUWzw5zydaRCqaaYw NpSIs+jLlpQk/hIo/f/DfoH18+H13uIf2BJCmrs= X-Google-Smtp-Source: AGHT+IFoL/Sqk6vInR+mOwkIJLAoc7daE5Ior/xfLIcnmoWupbL27htsqN3E2aPHpGfH64dWS31JhA== X-Received: by 2002:a1c:7206:0:b0:3fe:4cbc:c345 with SMTP id n6-20020a1c7206000000b003fe4cbcc345mr14096613wmc.41.1700205434169; Thu, 16 Nov 2023 23:17:14 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Subbaraya Sundeep , Arnaud Minier , Igor Mammedov , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Tyrone Ting , Hao Wu , Marcel Apfelbaum , Felipe Balbi , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Alistair Francis , Yanan Wang , Richard Henderson , Eduardo Habkost , Peter Maydell , Helge Deller , Subbaraya Sundeep , Alexandre Iooss , Gavin Shan Subject: [PATCH-for-8.2? v2 1/4] hw/core/machine: Constify MachineClass::valid_cpu_types[] Date: Fri, 17 Nov 2023 08:17:01 +0100 Message-ID: <20231117071704.35040-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231117071704.35040-1-philmd@linaro.org> References: <20231117071704.35040-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700205502733100003 From: Gavin Shan Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson [PMD: Constify HPPA machines, restrict valid_cpu_types to machine_class_init() handlers] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/boards.h | 2 +- hw/hppa/machine.c | 22 ++++++++++------------ hw/m68k/q800.c | 11 +++++------ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index a735999298..da85f86efb 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -273,7 +273,7 @@ struct MachineClass { bool has_hotpluggable_cpus; bool ignore_memory_transaction_failures; int numa_mem_align_shift; - const char **valid_cpu_types; + const char * const *valid_cpu_types; strList *allowed_dynamic_sysbus_devices; bool auto_enable_numa_with_memhp; bool auto_enable_numa_with_memdev; diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 9d08f39490..c8da7c18d5 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -672,19 +672,18 @@ static void hppa_nmi(NMIState *n, int cpu_index, Erro= r **errp) } } =20 -static const char *HP_B160L_machine_valid_cpu_types[] =3D { - TYPE_HPPA_CPU, - NULL -}; - static void HP_B160L_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + TYPE_HPPA_CPU, + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); NMIClass *nc =3D NMI_CLASS(oc); =20 mc->desc =3D "HP B160L workstation"; mc->default_cpu_type =3D TYPE_HPPA_CPU; - mc->valid_cpu_types =3D HP_B160L_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_B160L_init; mc->reset =3D hppa_machine_reset; mc->block_default_type =3D IF_SCSI; @@ -709,19 +708,18 @@ static const TypeInfo HP_B160L_machine_init_typeinfo = =3D { }, }; =20 -static const char *HP_C3700_machine_valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, - NULL -}; - static void HP_C3700_machine_init_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + TYPE_HPPA64_CPU, + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); NMIClass *nc =3D NMI_CLASS(oc); =20 mc->desc =3D "HP C3700 workstation"; mc->default_cpu_type =3D TYPE_HPPA64_CPU; - mc->valid_cpu_types =3D HP_C3700_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_C3700_init; mc->reset =3D hppa_machine_reset; mc->block_default_type =3D IF_SCSI; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 1d7cd5ff1c..83d1571d02 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -726,19 +726,18 @@ static GlobalProperty hw_compat_q800[] =3D { }; static const size_t hw_compat_q800_len =3D G_N_ELEMENTS(hw_compat_q800); =20 -static const char *q800_machine_valid_cpu_types[] =3D { - M68K_CPU_TYPE_NAME("m68040"), - NULL -}; - static void q800_machine_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] =3D { + M68K_CPU_TYPE_NAME("m68040"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "Macintosh Quadra 800"; mc->init =3D q800_machine_init; mc->default_cpu_type =3D M68K_CPU_TYPE_NAME("m68040"); - mc->valid_cpu_types =3D q800_machine_valid_cpu_types; + mc->valid_cpu_types =3D valid_cpu_types; mc->max_cpus =3D 1; mc->block_default_type =3D IF_SCSI; mc->default_ram_id =3D "m68k_mac.ram"; --=20 2.41.0 From nobody Wed Nov 27 04:52:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1700205490; cv=none; d=zohomail.com; s=zohoarc; b=QbzSgQJdqbDGuwJ04qfgxmQOGM7J6Cu1BGo4V3IfAmSPdGrdH10sBZrqJ7MD/6IpY4iG/oQdU/qpWHtU7l9Ktb5aPIePZ60MZqsOmaPzGa6TGFNl0BP9PhhD3qejoq2kErrufPRJYj6N507pLyjPRVhMTcPQrE/zQlZmVC8E4Gk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700205490; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[176.184.46.187]) by smtp.gmail.com with ESMTPSA id p17-20020a5d48d1000000b003316ad360c1sm692737wrs.24.2023.11.16.23.17.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Nov 2023 23:17:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700205440; x=1700810240; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vTMyslaK2WpZ4IP8gJyy1ZNuQ4oQ3pn0mQiB92seVWw=; b=N65RxRGe1Toc16bX0HPtzdCydLBhCQc5cCy6nuzqyDOPg/3B25nxNyYhcbP7L57wvE nQzkhSzhkns2yjd/bsDskGFo7rukF/TOMycCc2g+FY1K84ZpZn51HasM0+cB8YMSOUVL yViBRNG7AesJlz1zZcI6ZlSTpvlDhOjXqk7o9TAYu4eBtZWWREakB+A3lyMgtb0Waz1j 6v6QGAFxAwXc0cNUfYMv8PlXjDZK/JnPrY6nwrv/G4QghwH3dmxBcerfZNGrL6Cab5E4 j85vUtpn2Qk1IoL2btlz/V7yyHCdRyJDM/U3q+CxWfn6Zgogmfpxu7Dvw9Dh+AtHhw9u PH3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700205440; x=1700810240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vTMyslaK2WpZ4IP8gJyy1ZNuQ4oQ3pn0mQiB92seVWw=; b=EGH+AWpiTi6DMP+QOtViUYvINL8au5KZsCcb512HmC+OEKzKdLmd5EXkcWWA+GdONA Oux/hSFTSZqsOIJe/xLXyUqXu+naed24Jx/N2R46U0irmcy3JgnejmLvG6t7JzTTPHtK AN+P0azh52D8aL3pqOkBQLRd7zZLmzGQDPyo/nJ6Zq4OJmvxJ8PnlPH2x5QgXDmjoaX7 dLO8mIxp7a9RTKFAI21/z99biUyB3Jh0ZDqTM+btp1iJYbKcRbzAtVSOXA51vbBxAdbi kO2eJ0rTtGTx6L/Waj7l8U/6cu9Na6DF/Dg99vqQByWcP7CEDAS1PAWzWovvrtmD4CK0 L6MQ== X-Gm-Message-State: AOJu0YwD8mXlTfYNynGas6dbVP31sh0XXGa7pZflCvdiQK/xSDjgfg1f Azh2Qnj1TpZmFPiTxqBHl3e3bjKJ0ogXYPA1jPw= X-Google-Smtp-Source: AGHT+IGx1OXcNRYIKVfcGxLgYXQquYseANjrOpkXYRiN8JTT5C++zk+TPy5n+J7LqKPUGH3xausNGA== X-Received: by 2002:a5d:6da9:0:b0:331:41ef:61f2 with SMTP id u9-20020a5d6da9000000b0033141ef61f2mr14721992wrs.15.1700205440338; Thu, 16 Nov 2023 23:17:20 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Subbaraya Sundeep , Arnaud Minier , Igor Mammedov , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Tyrone Ting , Hao Wu , Marcel Apfelbaum , Felipe Balbi , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Alistair Francis , Yanan Wang , Richard Henderson , Eduardo Habkost , Peter Maydell , Helge Deller , Subbaraya Sundeep , Alexandre Iooss , Gavin Shan Subject: [PATCH-for-8.2? v2 2/4] hw/arm/stm32f405: Report error when incorrect CPU is used Date: Fri, 17 Nov 2023 08:17:02 +0100 Message-ID: <20231117071704.35040-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231117071704.35040-1-philmd@linaro.org> References: <20231117071704.35040-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700205492648100001 Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Gavin Shan --- include/hw/arm/stm32f405_soc.h | 4 ---- hw/arm/netduinoplus2.c | 7 ++++++- hw/arm/olimex-stm32-h405.c | 8 ++++++-- hw/arm/stm32f405_soc.c | 8 +------- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index c968ce3ab2..d15c03c4b5 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -51,11 +51,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) #define CCM_SIZE (64 * 1024) =20 struct STM32F405State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; =20 ARMv7MState armv7m; =20 diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c index 515c081605..2e58984947 100644 --- a/hw/arm/netduinoplus2.c +++ b/hw/arm/netduinoplus2.c @@ -44,7 +44,6 @@ static void netduinoplus2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -55,8 +54,14 @@ static void netduinoplus2_init(MachineState *machine) =20 static void netduinoplus2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc =3D "Netduino Plus 2 Machine (Cortex-M4)"; mc->init =3D netduinoplus2_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init) diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c index 3aa61c91b7..d793de7c97 100644 --- a/hw/arm/olimex-stm32-h405.c +++ b/hw/arm/olimex-stm32-h405.c @@ -47,7 +47,6 @@ static void olimex_stm32_h405_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F405_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,9 +57,14 @@ static void olimex_stm32_h405_init(MachineState *machine) =20 static void olimex_stm32_h405_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + mc->desc =3D "Olimex STM32-H405 (Cortex-M4)"; mc->init =3D olimex_stm32_h405_init; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mc->valid_cpu_types =3D valid_cpu_types; =20 /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size =3D 0; diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index cef23d7ee4..a65bbe298d 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -149,7 +149,7 @@ static void stm32f405_soc_realize(DeviceState *dev_soc,= Error **errp) =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -287,17 +287,11 @@ static void stm32f405_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("RNG", 0x50060800, 0x400); } =20 -static Property stm32f405_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f405_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f405_soc_realize; - device_class_set_props(dc, stm32f405_soc_properties); /* No vmstate or reset required: device has no internal state */ } =20 --=20 2.41.0 From nobody Wed Nov 27 04:52:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[176.184.46.187]) by smtp.gmail.com with ESMTPSA id t4-20020a5d4604000000b0032fbd0c7d04sm1417408wrq.55.2023.11.16.23.17.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Nov 2023 23:17:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700205447; x=1700810247; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NH5P5ZdsVBU0A7f/AHoAHis/E7XVaC6npXWaZcl7Gsk=; b=YZeqypqQ+np7QYxoeTfr8yg/OYs4B64DMFZmyNuuCVRFnBabFcdiJ8fh6IyYbuphxb XvcnTDkxGgqWpvzRXI1CHLB34b1K1tdDPBq7khWk6+sACMtcFez3EftMBMxp6FuJG3Ox k8G++LFf5tNKueXa50C6TF8ZQh3LmUP0NIBNs+L51k32G8nZIuaOuI18Ou002pEwFXBy WrG0XTwTo/emPKq6YVbYjBEZxLnyLyiNCd2KFPcBhkAOnMpF1sKaLm+M6Ic8HD7awxlv 2WYrlbOXgeDC+K4o05JdmOtZHxEpWWNApWku5eWB86gqJec29/nc+Pd6AkUoFqNgOHdU YHUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700205447; x=1700810247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NH5P5ZdsVBU0A7f/AHoAHis/E7XVaC6npXWaZcl7Gsk=; b=toxypK0a7PFiZxv7sCDJlF+fALrIr6y402Xa5zp2wD83cbS8opWHXV/0c/ANnSzl1Y /4B2w4xW0tuqWUh1VVFS9WLg8b7/W3oQrL/+412iIuCBE9Zzq4M4kDDq5AwlUdl3LKT7 vSOlL3B3O2oZmL2waF/VWeCSSsdqn2qmpCOsymMwV0rCJ2PkhfAZXN5iuaX9Uqi3w1Ic Mt6xs23KNpK0wVrnOmj1cZ7mjC2TXWnR51+3d1oyttl/cs0S4dRvBgFnHYxYy0HRxwnU mNlVJ4Pt0Murd4awUuqBCwaXff/DQe5YbCE9woRC5o7B5tmNodKjgkopK1RxW76ZURHX g/rQ== X-Gm-Message-State: AOJu0YzedMsqLYEf0TkLgSPy2Q6pIKJe3McNTm5zRthLzCiDXWM21gLs fVXl+MeZEiKgGNX6AgO5EphIWEjPVMZm8EGJch0= X-Google-Smtp-Source: AGHT+IHM2TyTPGZFJZD74exP7sZWxX7K4D8EOEUMaEakkkiaj1qUKG6TJmuh5nx/jLJshlJCGuZ45g== X-Received: by 2002:a05:6512:11eb:b0:507:a383:fe18 with SMTP id p11-20020a05651211eb00b00507a383fe18mr11716101lfs.40.1700205446406; Thu, 16 Nov 2023 23:17:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Subbaraya Sundeep , Arnaud Minier , Igor Mammedov , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Tyrone Ting , Hao Wu , Marcel Apfelbaum , Felipe Balbi , qemu-arm@nongnu.org, =?UTF-8?q?In=C3=A8s=20Varhol?= , Alistair Francis , Yanan Wang , Richard Henderson , Eduardo Habkost , Peter Maydell , Helge Deller , Subbaraya Sundeep , Alexandre Iooss , Gavin Shan Subject: [PATCH-for-8.2? v2 3/4] hw/arm/stm32f205: Report error when incorrect CPU is used Date: Fri, 17 Nov 2023 08:17:03 +0100 Message-ID: <20231117071704.35040-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231117071704.35040-1-philmd@linaro.org> References: <20231117071704.35040-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=philmd@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700205508629100001 The 'netduino2' machine ignores the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-arm -M netduino2 -cpu cortex-a9 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-arm -M netduino2 -cpu cortex-a9 qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan --- include/hw/arm/stm32f205_soc.h | 4 ---- hw/arm/netduino2.c | 7 ++++++- hw/arm/stm32f205_soc.c | 9 ++------- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 5a4f776264..4f4c8bbebc 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -49,11 +49,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F205State, STM32F205_SOC) #define SRAM_SIZE (128 * 1024) =20 struct STM32F205State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ - - char *cpu_type; =20 ARMv7MState armv7m; =20 diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 83753d53a3..501f63a77f 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -44,7 +44,6 @@ static void netduino2_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F205_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -54,8 +53,14 @@ static void netduino2_init(MachineState *machine) =20 static void netduino2_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "Netduino 2 Machine (Cortex-M3)"; mc->init =3D netduino2_init; + mc->valid_cpu_types =3D valid_cpu_types; mc->ignore_memory_transaction_failures =3D true; } =20 diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index c6b75a381d..1a548646f6 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -127,7 +127,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc,= Error **errp) =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -201,17 +201,12 @@ static void stm32f205_soc_realize(DeviceState *dev_so= c, Error **errp) } } =20 -static Property stm32f205_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f205_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f205_soc_realize; - device_class_set_props(dc, stm32f205_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f205_soc_info =3D { --=20 2.41.0 From nobody Wed Nov 27 04:52:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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This might confuse users, since the following will create a machine with a Cortex-M3 CPU: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1 qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu The valid types are: cortex-m3-arm-cpu Since the SoC family can only use Cortex-M3 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gavin Shan --- include/hw/arm/stm32f100_soc.h | 4 ---- hw/arm/stm32f100_soc.c | 9 ++------- hw/arm/stm32vldiscovery.c | 7 ++++++- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h index 40cd415b28..a74d7b369c 100644 --- a/include/hw/arm/stm32f100_soc.h +++ b/include/hw/arm/stm32f100_soc.h @@ -43,12 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) #define SRAM_SIZE (8 * 1024) =20 struct STM32F100State { - /*< private >*/ SysBusDevice parent_obj; =20 - /*< public >*/ - char *cpu_type; - ARMv7MState armv7m; =20 STM32F2XXUsartState usart[STM_NUM_USARTS]; diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index f7b344ba9f..b90d440d7a 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -115,7 +115,7 @@ static void stm32f100_soc_realize(DeviceState *dev_soc,= Error **errp) /* Init ARMv7m */ armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 61); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"= )); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -180,17 +180,12 @@ static void stm32f100_soc_realize(DeviceState *dev_so= c, Error **errp) create_unimplemented_device("CRC", 0x40023000, 0x400); } =20 -static Property stm32f100_soc_properties[] =3D { - DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), - DEFINE_PROP_END_OF_LIST(), -}; - static void stm32f100_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D stm32f100_soc_realize; - device_class_set_props(dc, stm32f100_soc_properties); + /* No vmstate or reset required: device has no internal state */ } =20 static const TypeInfo stm32f100_soc_info =3D { diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c index 67675e952f..190db6118b 100644 --- a/hw/arm/stm32vldiscovery.c +++ b/hw/arm/stm32vldiscovery.c @@ -47,7 +47,6 @@ static void stm32vldiscovery_init(MachineState *machine) clock_set_hz(sysclk, SYSCLK_FRQ); =20 dev =3D qdev_new(TYPE_STM32F100_SOC); - qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_connect_clock_in(dev, "sysclk", sysclk); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -58,8 +57,14 @@ static void stm32vldiscovery_init(MachineState *machine) =20 static void stm32vldiscovery_machine_init(MachineClass *mc) { + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m3"), + NULL + }; + mc->desc =3D "ST STM32VLDISCOVERY (Cortex-M3)"; mc->init =3D stm32vldiscovery_init; + mc->valid_cpu_types =3D valid_cpu_types; } =20 DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) --=20 2.41.0