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Wed, 15 Nov 2023 15:22:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Arnaud Minier , =?UTF-8?q?In=C3=A8s=20Varhol?= , Tyrone Ting , Subbaraya Sundeep , Hao Wu , Felipe Balbi , Gavin Shan , Igor Mammedov , Subbaraya Sundeep , Peter Maydell , Eduardo Habkost , Alistair Francis , Alexandre Iooss , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-9.0 6/6] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] Date: Thu, 16 Nov 2023 00:21:53 +0100 Message-ID: <20231115232154.4515-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231115232154.4515-1-philmd@linaro.org> References: <20231115232154.4515-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1700090646417100007 Musca boards use the embedded subsystems (SSE) tied to a specific Cortex core. Our models only use the Cortex-M33. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Remove the now unused MachineClass::default_cpu_type field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/musca.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 6eeee57c9d..d3658354ba 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -355,7 +355,6 @@ static void musca_init(MachineState *machine) { MuscaMachineState *mms =3D MUSCA_MACHINE(machine); MuscaMachineClass *mmc =3D MUSCA_MACHINE_GET_CLASS(mms); - MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *ssedev; DeviceState *dev_splitter; @@ -366,12 +365,6 @@ static void musca_init(MachineState *machine) assert(mmc->num_irqs <=3D MUSCA_NUMIRQ_MAX); assert(mmc->num_mpcs <=3D MUSCA_MPC_MAX); =20 - if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { - error_report("This board can only be used with CPU %s", - mc->default_cpu_type); - exit(1); - } - mms->sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); clock_set_hz(mms->sysclk, SYSCLK_FRQ); mms->s32kclk =3D clock_new(OBJECT(machine), "S32KCLK"); @@ -603,12 +596,16 @@ static void musca_init(MachineState *machine) =20 static void musca_class_init(ObjectClass *oc, void *data) { + static const char *machine_valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m33"), + NULL + }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->default_cpus =3D 2; mc->min_cpus =3D mc->default_cpus; mc->max_cpus =3D mc->default_cpus; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->valid_cpu_types =3D machine_valid_cpu_types; mc->init =3D musca_init; } =20 --=20 2.41.0