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[61.230.7.62]) by smtp.gmail.com with ESMTPSA id r2-20020aa78b82000000b006c871f3ad1csm1443496pfd.71.2023.11.15.06.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1700058826; x=1700663626; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/+LSBBFvRHoLXmzEGwmfH2B1p6OS5SltGOhUI11MSx0=; b=FrX57pk2UlPjS1hlaVE+pCCFCtXm9oVCn509PbxcF5fpnNzk6V9fJKvHr1s9esvIIZ kwrLn8VwPAOBjybs6dqrJHVD5ZUHUjc9wSaOGpwwMv+vcweNwjDZLgOHKj/e8xOP7Ppu CZM1Wqx4aNyAcSCndOyDdVKOl+AlPxxAEW9y3hqqvMMuoI9GhBC3Eq36OXpqZlm2yhX+ IOSmvL/xavrtrRi+hr9zyKesOyVHdiZJdwORj8zLunEGHoYlMkFiyw/VuGCKOKZsNmCC eX0phnxepMALU9GrYf03E+3lYgEwDTZt23VOSz/vRGUe9zTDXKUipPPnVuyJlceRo45d NtEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058826; x=1700663626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/+LSBBFvRHoLXmzEGwmfH2B1p6OS5SltGOhUI11MSx0=; b=d3O/RP7KXImEhYdBR8POvWJtDd8ZpPyiG9B8gvLZIJnLbnzmMQ2nkUEsQwVzmM4tIv J3vLGMGciIFk3i1Ze8/TKCAfuOaqkebNCyaqrwfqgJYNCF+93TMmlhC/rhw8VRVNwem8 AMR1nRoiORpTJlvWkd+8LfVyIp9NgJtgK9ZQcQA/wpwhe8B+0SPnwPCZWu3LG3lZwyG3 W98b/SSN9iBPYGLgXHq0TwxoOOWHbnLPFTZs7fnjMW0c9sgx2ouvCBrpkisi+mKvWQVq g9yClk/aJYah38VUieH7FjsQvxTUZp/WiYqb5ukY+m6Kz3Tc+shAGPcY7i3d1M+4HVMe H4fw== X-Gm-Message-State: AOJu0Yxgo/UaMfGXtRnSiKik3G65TP0Vz2f4KA6c1eMEWY8yQD4S0VrY gStx2/2i4lXn+evyLgkJrrib0w== X-Google-Smtp-Source: AGHT+IFw8svGTcpZWXRBqnIQRltTgT/wseGybtQH+90D6HQxtCy2e7TkYszhWjlGArUWzEPt3BAiCg== X-Received: by 2002:a05:6a00:2d95:b0:6be:e54e:a540 with SMTP id fb21-20020a056a002d9500b006bee54ea540mr15264914pfb.30.1700058826407; Wed, 15 Nov 2023 06:33:46 -0800 (PST) From: Max Hsu To: Peter Maydell , Andrey Smirnov Cc: Frank Chang , qemu-arm@nongnu.org, Greentime Hu , qemu-devel@nongnu.org, Max Hsu Subject: [PATCH 1/2] hw/pci-host: Designware: Fix inbound iATU no address match behavior Date: Wed, 15 Nov 2023 22:33:40 +0800 Message-Id: <20231115143341.13068-2-max.hsu@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231115143341.13068-1-max.hsu@sifive.com> References: <20231115143341.13068-1-max.hsu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=max.hsu@sifive.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1700058889432100004 Content-Type: text/plain; charset="utf-8" IMX6DQRM Rev4, in chapter 48.3.9.3, specifies that for inbound iATU with no address match: 'If there is no match, then the address is untranslated.' The current model implementation registers inbound region 0 as untranslated dummy, intending to serve as a passing medium for the no-match address behavior using MemoryRegion. However, a bug exists where the Linux Kernel driver of Designware PCIe RC is unaware that inbound region 0 is registered for special setup. During Kernel driver initialization, the driver overwrites the target address to 0x1111_0000 and later disables all regions, rendering the untranslated passing medium ineffective. Consequently, TLP cannot pass iATU, and the transaction is blocked. To address this issue, we propose "inbound untranslated pass" which is consistently enabled and distinct from the usage of iATU regions. We achieve this by introducing a new MemoryRegion with the lowest priority to prevent conflicts with configured iATU regions. This fix has been tested with the integration of Designware PCIe RC along with the e1000e Ethernet card, ensuring proper functioning of network transmissions and MSI interrupts. Signed-off-by: Max Hsu --- hw/pci-host/designware.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index f477f97847..83dd9b1aaf 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -487,17 +487,28 @@ static void designware_pcie_root_realize(PCIDevice *d= ev, Error **errp) } =20 /* - * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by explicitly - * configuring first inbound window to cover all of target's - * address space. + * For HW iATU address no match behavior, the TLP should continue with + * untranslated address. * - * NOTE: This will not work correctly for the case when first - * configured inbound window is window 0 + * We emulate this behavior by adding extra MemoryRegions to create a + * 1:1 mapping between PCI address space and cpu address space within + * the 64-bit range, encompassing both inbound and outbound directions. + * + * To avoid interfering with the configured iATU regions and potential= ly + * producing incorrect addresses, the two untranslated regions are set + * to have the lowest priority. */ - viewport =3D &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; - viewport->cr[1] =3D DESIGNWARE_PCIE_ATU_ENABLE; - designware_pcie_update_viewport(root, viewport); + MemoryRegion *inbound_untranslated =3D g_new(MemoryRegion, 1); + + memory_region_init_alias(inbound_untranslated, OBJECT(root), + "inbound untranslated pass", + get_system_memory(), dummy_offset, dummy_size= ); + memory_region_add_subregion_overlap(&host->pci.address_space_root, + dummy_offset, inbound_untranslated, + INT32_MIN); + memory_region_set_size(inbound_untranslated, UINT64_MAX); + memory_region_set_address(inbound_untranslated, 0x0ULL); + memory_region_set_enabled(inbound_untranslated, true); =20 memory_region_init_io(&root->msi.iomem, OBJECT(root), &designware_pci_host_msi_ops, --=20 2.34.1