From nobody Wed Nov 27 08:44:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1700032707; cv=none; d=zohomail.com; s=zohoarc; b=mBboq3zifqU5Ezk13wkR4M0N4FOkIxqMFqbL9bIXmwuP4jjFz/dnJcZPW85CPEafC1HRpvrfrJs6Me8YoV/eANT/wWAFTbs0OH1P/Nfl6eAvK9c3O9BkdyaQD6XnyqgWRqyILlP/tYq4NuiMH4eeGXYVZr5VEi50L/RkSOULaWk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700032707; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7Sjz0IhO107yKYxFpfsWHIMRDGCq3z7uLAdux5BbBDU=; b=E4f+4cX/U/Gw4lsKew1j556xCg+67wnFDkd3NkpqZq9qwX2GYLmCE0r0nd2uuS3Utsq+E7xeqC8fDnAxUZKkWDVZpkfmvYjvIq372JjFbkpO6TxHmU2Xl6pprzL3lfiZOdcQUpIT6tWPAs4HHa0grCQm8jVaeDjJ3mHzfmfN7YQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700032707405865.9676749600167; Tue, 14 Nov 2023 23:18:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r3AAE-00064E-Te; Wed, 15 Nov 2023 02:18:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3AAD-0005qr-2r for qemu-devel@nongnu.org; Wed, 15 Nov 2023 02:18:17 -0500 Received: from mgamail.intel.com ([192.55.52.115]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r3AA9-0002U6-7F for qemu-devel@nongnu.org; Wed, 15 Nov 2023 02:18:15 -0500 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2023 23:18:11 -0800 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orsmga003.jf.intel.com with ESMTP; 14 Nov 2023 23:18:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700032693; x=1731568693; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q/vGUcTjmW3xLkhpTgJb1cHgy5ooIIHzznjqzU/8EUA=; b=Dz4YluU+D5HzhdzfwbHBsotz9uKBCtevYLlEJu1L/Q28QxCDUxwXMDTs hZAgF3A3ROWD3Gc8TuTVvVuXWU/mZ82NX2lWqXtRCytR51XYJNmI7/zVx fHzWuRNNzisqjOs5r8rYZvwqzdMFwnMfEKjhf3JI+TZAUGliLfy0pbJGs JfR61qfbLTwdPUTeFES4w6WPwPBjx35YN/JpXwm66eHt0gpMsaXC9CyGK Q9A2TccDkvxhAUAeZBB67fdlKO0jyFdpewA1EdE/qXVKv0GK5ojcuHP1f cXRGisxSMhbQ0c2xcQjKmSr8t3XOYSh4DHW4FTny1p/dcSl2dnDIBS09v A==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="390622717" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="390622717" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="714798324" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="714798324" From: Xiaoyao Li To: Paolo Bonzini , David Hildenbrand , Igor Mammedov , "Michael S . Tsirkin" , Marcel Apfelbaum , Richard Henderson , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com, Michael Roth , Sean Christopherson , Claudio Fontana , Gerd Hoffmann , Isaku Yamahata , Chenyi Qiang Subject: [PATCH v3 24/70] i386/kvm: Move architectural CPUID leaf generation to separate helper Date: Wed, 15 Nov 2023 02:14:33 -0500 Message-Id: <20231115071519.2864957-25-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231115071519.2864957-1-xiaoyao.li@intel.com> References: <20231115071519.2864957-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1700032709362100003 Content-Type: text/plain; charset="utf-8" From: Sean Christopherson Move the architectural (for lack of a better term) CPUID leaf generation to a separate helper so that the generation code can be reused by TDX, which needs to generate a canonical VM-scoped configuration. Signed-off-by: Sean Christopherson Signed-off-by: Xiaoyao Li --- target/i386/kvm/kvm.c | 454 +++++++++++++++++++------------------ target/i386/kvm/kvm_i386.h | 3 + 2 files changed, 235 insertions(+), 222 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f2627dd61d2b..dafe4d262977 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1733,6 +1733,236 @@ static void kvm_init_nested_state(CPUX86State *env) } } =20 +uint32_t kvm_x86_arch_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *ent= ries, + uint32_t cpuid_i) +{ + uint32_t limit, i, j; + uint32_t unused; + struct kvm_cpuid_entry2 *c; + + cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); + + for (i =3D 0; i <=3D limit; i++) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "unsupported level value: 0x%x\n", limit); + abort(); + } + c =3D &entries[cpuid_i++]; + + switch (i) { + case 2: { + /* Keep reading function 2 till all the input is received */ + int times; + + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_STATEFUL_FUNC | + KVM_CPUID_FLAG_STATE_READ_NEXT; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + times =3D c->eax & 0xff; + + for (j =3D 1; j < times; ++j) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:2):eax & 0xf =3D 0x%x\n", times); + abort(); + } + c =3D &entries[cpuid_i++]; + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_STATEFUL_FUNC; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + } + break; + } + case 0x1f: + if (env->nr_dies < 2) { + cpuid_i--; + break; + } + /* fallthrough */ + case 4: + case 0xb: + case 0xd: + for (j =3D 0; ; j++) { + if (i =3D=3D 0xd && j =3D=3D 64) { + break; + } + + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index =3D j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + + if (i =3D=3D 4 && c->eax =3D=3D 0) { + break; + } + if (i =3D=3D 0xb && !(c->ecx & 0xff00)) { + break; + } + if (i =3D=3D 0x1f && !(c->ecx & 0xff00)) { + break; + } + if (i =3D=3D 0xd && c->eax =3D=3D 0) { + continue; + } + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c =3D &entries[cpuid_i++]; + } + break; + case 0x7: + case 0x12: + for (j =3D 0; ; j++) { + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index =3D j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + + if (j > 1 && (c->eax & 0xf) !=3D 1) { + break; + } + + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x12,ecx:0x%x)\n", j); + abort(); + } + c =3D &entries[cpuid_i++]; + } + break; + case 0x14: + case 0x1d: + case 0x1e: { + uint32_t times; + + c->function =3D i; + c->index =3D 0; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + times =3D c->eax; + + for (j =3D 1; j <=3D times; ++j) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c =3D &entries[cpuid_i++]; + c->function =3D i; + c->index =3D j; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + } + break; + } + default: + c->function =3D i; + c->flags =3D 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + if (!c->eax && !c->ebx && !c->ecx && !c->edx) { + /* + * KVM already returns all zeroes if a CPUID entry is miss= ing, + * so we can omit it and avoid hitting KVM's 80-entry limi= t. + */ + cpuid_i--; + } + break; + } + } + + if (limit >=3D 0x0a) { + uint32_t eax, edx; + + cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); + + has_architectural_pmu_version =3D eax & 0xff; + if (has_architectural_pmu_version > 0) { + num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; + + /* Shouldn't be more than 32, since that's the number of bits + * available in EBX to tell us _which_ counters are available. + * Play it safe. + */ + if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { + num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + } + + if (has_architectural_pmu_version > 1) { + num_architectural_pmu_fixed_counters =3D edx & 0x1f; + + if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNT= ERS) { + num_architectural_pmu_fixed_counters =3D MAX_FIXED_COU= NTERS; + } + } + } + } + + cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); + + for (i =3D 0x80000000; i <=3D limit; i++) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); + abort(); + } + c =3D &entries[cpuid_i++]; + + switch (i) { + case 0x8000001d: + /* Query for all AMD cache information leaves */ + for (j =3D 0; ; j++) { + c->function =3D i; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + c->index =3D j; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + + if (c->eax =3D=3D 0) { + break; + } + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); + abort(); + } + c =3D &entries[cpuid_i++]; + } + break; + default: + c->function =3D i; + c->flags =3D 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + if (!c->eax && !c->ebx && !c->ecx && !c->edx) { + /* + * KVM already returns all zeroes if a CPUID entry is miss= ing, + * so we can omit it and avoid hitting KVM's 80-entry limi= t. + */ + cpuid_i--; + } + break; + } + } + + /* Call Centaur's CPUID instructions they are supported. */ + if (env->cpuid_xlevel2 > 0) { + cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unuse= d); + + for (i =3D 0xC0000000; i <=3D limit; i++) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit= ); + abort(); + } + c =3D &entries[cpuid_i++]; + + c->function =3D i; + c->flags =3D 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + } + } + + return cpuid_i; +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -1749,8 +1979,7 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; - uint32_t limit, i, j, cpuid_i; - uint32_t unused; + uint32_t cpuid_i; struct kvm_cpuid_entry2 *c; uint32_t signature[3]; int kvm_base =3D KVM_CPUID_SIGNATURE; @@ -1903,8 +2132,6 @@ int kvm_arch_init_vcpu(CPUState *cs) c->edx =3D env->features[FEAT_KVM_HINTS]; } =20 - cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); - if (cpu->kvm_pv_enforce_cpuid) { r =3D kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0,= 1); if (r < 0) { @@ -1915,224 +2142,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - for (i =3D 0; i <=3D limit; i++) { - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "unsupported level value: 0x%x\n", limit); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - - switch (i) { - case 2: { - /* Keep reading function 2 till all the input is received */ - int times; - - c->function =3D i; - c->flags =3D KVM_CPUID_FLAG_STATEFUL_FUNC | - KVM_CPUID_FLAG_STATE_READ_NEXT; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); - times =3D c->eax & 0xff; - - for (j =3D 1; j < times; ++j) { - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:2):eax & 0xf =3D 0x%x\n", times); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D i; - c->flags =3D KVM_CPUID_FLAG_STATEFUL_FUNC; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->ed= x); - } - break; - } - case 0x1f: - if (env->nr_dies < 2) { - cpuid_i--; - break; - } - /* fallthrough */ - case 4: - case 0xb: - case 0xd: - for (j =3D 0; ; j++) { - if (i =3D=3D 0xd && j =3D=3D 64) { - break; - } - - c->function =3D i; - c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - c->index =3D j; - cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); - - if (i =3D=3D 4 && c->eax =3D=3D 0) { - break; - } - if (i =3D=3D 0xb && !(c->ecx & 0xff00)) { - break; - } - if (i =3D=3D 0x1f && !(c->ecx & 0xff00)) { - break; - } - if (i =3D=3D 0xd && c->eax =3D=3D 0) { - continue; - } - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - } - break; - case 0x7: - case 0x12: - for (j =3D 0; ; j++) { - c->function =3D i; - c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - c->index =3D j; - cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); - - if (j > 1 && (c->eax & 0xf) !=3D 1) { - break; - } - - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x12,ecx:0x%x)\n", j); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - } - break; - case 0x14: - case 0x1d: - case 0x1e: { - uint32_t times; - - c->function =3D i; - c->index =3D 0; - c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); - times =3D c->eax; - - for (j =3D 1; j <=3D times; ++j) { - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D i; - c->index =3D j; - c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); - } - break; - } - default: - c->function =3D i; - c->flags =3D 0; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); - if (!c->eax && !c->ebx && !c->ecx && !c->edx) { - /* - * KVM already returns all zeroes if a CPUID entry is miss= ing, - * so we can omit it and avoid hitting KVM's 80-entry limi= t. - */ - cpuid_i--; - } - break; - } - } - - if (limit >=3D 0x0a) { - uint32_t eax, edx; - - cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); - - has_architectural_pmu_version =3D eax & 0xff; - if (has_architectural_pmu_version > 0) { - num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; - - /* Shouldn't be more than 32, since that's the number of bits - * available in EBX to tell us _which_ counters are available. - * Play it safe. - */ - if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; - } - - if (has_architectural_pmu_version > 1) { - num_architectural_pmu_fixed_counters =3D edx & 0x1f; - - if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNT= ERS) { - num_architectural_pmu_fixed_counters =3D MAX_FIXED_COU= NTERS; - } - } - } - } - - cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); - - for (i =3D 0x80000000; i <=3D limit; i++) { - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - - switch (i) { - case 0x8000001d: - /* Query for all AMD cache information leaves */ - for (j =3D 0; ; j++) { - c->function =3D i; - c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; - c->index =3D j; - cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); - - if (c->eax =3D=3D 0) { - break; - } - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - } - break; - default: - c->function =3D i; - c->flags =3D 0; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); - if (!c->eax && !c->ebx && !c->ecx && !c->edx) { - /* - * KVM already returns all zeroes if a CPUID entry is miss= ing, - * so we can omit it and avoid hitting KVM's 80-entry limi= t. - */ - cpuid_i--; - } - break; - } - } - - /* Call Centaur's CPUID instructions they are supported. */ - if (env->cpuid_xlevel2 > 0) { - cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unuse= d); - - for (i =3D 0xC0000000; i <=3D limit; i++) { - if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { - fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit= ); - abort(); - } - c =3D &cpuid_data.entries[cpuid_i++]; - - c->function =3D i; - c->flags =3D 0; - cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); - } - } - + cpuid_i =3D kvm_x86_arch_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent =3D cpuid_i; =20 if (((env->cpuid_version >> 8)&0xF) >=3D 6 diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index c3ef46a97a7b..cbf52c1c6d17 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -24,6 +24,9 @@ #define kvm_ioapic_in_kernel() \ (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split()) =20 +uint32_t kvm_x86_arch_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *ent= ries, + uint32_t cpuid_i); + #else =20 #define kvm_pit_in_kernel() 0 --=20 2.34.1