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bh=OA60zNYm3MxVJu1zn1Aljj0URKLh8YnKa9eMWyVPTBc=; b=Wa9pCYA2cBpX4xa8lLGclb9tSwnr9ZR+LQk0hAL9Z7o+DGapcr3wjLS9uP3CwozAekJrha dwxZu4/2rlC0sQXolYdSkr5FWdZygeGoRFCQkyfwODCTgA42d0/7tsIppe0PC2hIGhk5fs 0s50RwOWNHSLTPS1gizbGAcSe3aul5c= X-MC-Unique: 8-4GrtLFNIyl9bRUcLom5w-1 From: Gavin Shan To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, richard.henderson@linaro.org, pbonzini@redhat.com, peter.maydell@linaro.org, imammedo@redhat.com, philmd@linaro.org, b.galvani@gmail.com, strahinja.p.jankovic@gmail.com, sundeep.lkml@gmail.com, kfting@nuvoton.com, wuhaotsh@google.com, nieklinnenbank@gmail.com, rad@semihalf.com, quic_llindhol@quicinc.com, marcin.juszkiewicz@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, laurent@vivier.eu, vijai@behindbytes.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, mrolnik@gmail.com, edgar.iglesias@gmail.com, bcain@quicinc.com, gaosong@loongson.cn, aurelien@aurel32.net, jiaxun.yang@flygoat.com, aleksandar.rikalo@syrmia.com, chenhuacai@kernel.org, shorne@gmail.com, npiggin@gmail.com, clg@kaod.org, ysato@users.sourceforge.jp, kbastian@mail.uni-paderborn.de, jcmvbkbc@gmail.com, shan.gavin@gmail.com Subject: [PATCH v5 08/31] target/arm: Use generic cpu_list() Date: Wed, 15 Nov 2023 09:56:05 +1000 Message-ID: <20231114235628.534334-9-gshan@redhat.com> In-Reply-To: <20231114235628.534334-1-gshan@redhat.com> References: <20231114235628.534334-1-gshan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" No changes of the output from the following command before and after it's applied. [gshan@gshan q]$ ./build/qemu-system-aarch64 -cpu ? Available CPUs: a64fx arm1026 arm1136 arm1136-r2 arm1176 arm11mpcore arm926 arm946 cortex-a15 cortex-a35 cortex-a53 cortex-a55 cortex-a57 cortex-a7 cortex-a710 cortex-a72 cortex-a76 cortex-a8 cortex-a9 cortex-m0 cortex-m3 cortex-m33 cortex-m4 cortex-m55 cortex-m7 cortex-r5 cortex-r52 cortex-r5f max neoverse-n1 neoverse-n2 neoverse-v1 pxa250 pxa255 pxa260 pxa261 pxa262 pxa270-a0 pxa270-a1 pxa270 pxa270-b0 pxa270-b1 pxa270-c0 pxa270-c5 sa1100 sa1110 ti925t Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 --- target/arm/helper.c | 46 --------------------------------------------- 2 files changed, 49 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d28..8c3ca2e231 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2737,7 +2737,6 @@ static inline bool access_secure_reg(CPUARMState *env) (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))= , \ (_val)) =20 -void arm_cpu_list(void); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); =20 @@ -2840,8 +2839,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); =20 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU =20 -#define cpu_list arm_cpu_list - /* ARM has the following "translation regimes" (as the ARM ARM calls them): * * If EL3 is 64-bit: diff --git a/target/arm/helper.c b/target/arm/helper.c index ff1970981e..c9a8baefc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9421,52 +9421,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif } =20 -/* Sort alphabetically by type name, except for "any". */ -static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a =3D (ObjectClass *)a; - ObjectClass *class_b =3D (ObjectClass *)b; - const char *name_a, *name_b; - - name_a =3D object_class_get_name(class_a); - name_b =3D object_class_get_name(class_b); - if (strcmp(name_a, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return 1; - } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return -1; - } else { - return strcmp(name_a, name_b); - } -} - -static void arm_cpu_list_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc =3D data; - CPUClass *cc =3D CPU_CLASS(oc); - const char *typename; - char *name; - - typename =3D object_class_get_name(oc); - name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CP= U)); - if (cc->deprecation_note) { - qemu_printf(" %s (deprecated)\n", name); - } else { - qemu_printf(" %s\n", name); - } - g_free(name); -} - -void arm_cpu_list(void) -{ - GSList *list; - - list =3D object_class_get_list(TYPE_ARM_CPU, false); - list =3D g_slist_sort(list, arm_cpu_list_compare); - qemu_printf("Available CPUs:\n"); - g_slist_foreach(list, arm_cpu_list_entry, NULL); - g_slist_free(list); -} - /* * Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. --=20 2.41.0