From nobody Wed Nov 27 09:40:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699955357; cv=none; d=zohomail.com; s=zohoarc; b=T0trXlEfGDhJi/PyYMcsv5BHYUBPdJ1e+85yN7OWsnuJw/u53vEOQGktaGpF6SPQbhgP76+y+A2z0CpasKGvoPmUv9oy/JWGT3DCz161QYRntfQjtfP6GZX4e3GLxb8IJIOteSuBWasih4XwBs/eJ3Yv7WUaF+67iRc9soQRkdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699955357; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=guNF/ythmS2z47YLFu2U0dOgdZyzUw2kB40gP7wHjss=; b=a+gwBXcCKkUwkjP9P4VXZvMRmgEplUyxWYrfoIrN3NwQKj2Q8BAm5pp26VXPNPahHIHGVEMfbEEKp9kEe7bsvz+3nSYbp1oeX2lLLbl8SLYwDyTZuC52G5MCIwS9ANbNeW1gJLRO2fnL87LW3GnPSmqWvfovnh0KC4dq25naGHw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699955357128257.38350456366834; Tue, 14 Nov 2023 01:49:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2q1d-0005Sx-G3; Tue, 14 Nov 2023 04:48:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2q1b-0005Q4-Mr; Tue, 14 Nov 2023 04:48:03 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2q1Z-00012k-HV; Tue, 14 Nov 2023 04:48:03 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AE9lbKI081681; Tue, 14 Nov 2023 17:47:37 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox.andestech.com (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 14 Nov 2023 17:47:33 +0800 To: CC: , , , , , , , , , , , , , Ethan Chen Subject: [PATCH v3 4/4] hw/riscv/virt: Add IOPMP support Date: Tue, 14 Nov 2023 17:47:05 +0800 Message-ID: <20231114094705.109146-5-ethan84@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114094705.109146-1-ethan84@andestech.com> References: <20231114094705.109146-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.51] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3AE9lbKI081681 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1699955358771100001 Content-Type: text/plain; charset="utf-8" - Add 'iopmp=3Don' option to enable a iopmp device and a dma device connect to the iopmp device - Add 'iopmp_cascade=3Don' option to enable iopmp cascading. Signed-off-by: Ethan Chen --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt.c | 72 +++++++++++++++++++++++++++++++++++++++-- include/hw/riscv/virt.h | 10 +++++- 3 files changed, 81 insertions(+), 3 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index b6a5eb4452..c30a104aa4 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -45,6 +45,8 @@ config RISCV_VIRT select FW_CFG_DMA select PLATFORM_BUS select ACPI + select ATCDMAC300 + select RISCV_IOPMP =20 config SHAKTI_C bool diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c7fc97e273..3e23ee3afc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -53,6 +53,8 @@ #include "hw/display/ramfb.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" +#include "hw/misc/riscv_iopmp.h" +#include "hw/dma/atcdmac300.h" =20 /* * The virt machine physical address space used by some of the devices @@ -97,6 +99,9 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, + [VIRT_IOPMP] =3D { 0x10200000, 0x100000 }, + [VIRT_IOPMP2] =3D { 0x10300000, 0x100000 }, + [VIRT_DMAC] =3D { 0x10400000, 0x100000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, [VIRT_IMSIC_M] =3D { 0x24000000, VIRT_IMSIC_MAX_SIZE }, [VIRT_IMSIC_S] =3D { 0x28000000, VIRT_IMSIC_MAX_SIZE }, @@ -1527,13 +1532,33 @@ static void virt_machine_init(MachineState *machine) =20 create_platform_bus(s, mmio_irqchip); =20 - serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, + serial_mm_init(system_memory, memmap[VIRT_UART0].base + 0x20, + 0x2, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); =20 + /* DMAC */ + DeviceState *dmac_dev =3D atcdmac300_create("atcdmac300", + memmap[VIRT_DMAC].base, memmap[VIRT_DMAC].size, + qdev_get_gpio_in(DEVICE(mmio_irqchip), DMAC_IRQ)); + + if (s->have_iopmp) { + /* IOPMP */ + DeviceState *iopmp_dev =3D iopmp_create(memmap[VIRT_IOPMP].base, + qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP_IRQ)); + /* DMA with IOPMP */ + atcdmac300_connect_iopmp(dmac_dev, &(IOPMP(iopmp_dev)->iopmp_as), + (StreamSink *)&(IOPMP(iopmp_dev)->transaction_info_sink), 0); + if (s->have_iopmp_cascade) { + DeviceState *iopmp_dev2 =3D iopmp_create(memmap[VIRT_IOPMP2].b= ase, + qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP2_IRQ)); + cascade_iopmp(iopmp_dev, iopmp_dev2); + } + } + + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { /* Map legacy -drive if=3Dpflash to machine properties */ pflash_cfi01_legacy_drive(s->flash[i], @@ -1628,6 +1653,35 @@ static void virt_set_aclint(Object *obj, bool value,= Error **errp) s->have_aclint =3D value; } =20 +static bool virt_get_iopmp(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_iopmp; +} + +static void virt_set_iopmp(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_iopmp =3D value; +} + +static bool virt_get_iopmp_cascade(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_iopmp_cascade; +} + +static void virt_set_iopmp_cascade(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_iopmp_cascade =3D value; +} + + bool virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi !=3D ON_OFF_AUTO_OFF; @@ -1730,6 +1784,20 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) NULL, NULL); object_class_property_set_description(oc, "acpi", "Enable ACPI"); + + object_class_property_add_bool(oc, "iopmp", virt_get_iopmp, + virt_set_iopmp); + object_class_property_set_description(oc, "iopmp", + "Set on/off to enable/disable " + "iopmp device"); + + object_class_property_add_bool(oc, "iopmp-cascade", + virt_get_iopmp_cascade, + virt_set_iopmp_cascade); + object_class_property_set_description(oc, "iopmp-cascade", + "Set on/off to enable/disable " + "iopmp2 device which is cascaded= by " + "iopmp1 device"); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e5c474b26e..5fa2944d29 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -54,6 +54,8 @@ struct RISCVVirtState { =20 int fdt_size; bool have_aclint; + bool have_iopmp; + bool have_iopmp_cascade; RISCVVirtAIAType aia_type; int aia_guests; char *oem_id; @@ -82,12 +84,18 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PLATFORM_BUS, - VIRT_PCIE_ECAM + VIRT_PCIE_ECAM, + VIRT_IOPMP, + VIRT_IOPMP2, + VIRT_DMAC, }; =20 enum { UART0_IRQ =3D 10, RTC_IRQ =3D 11, + DMAC_IRQ =3D 12, + IOPMP_IRQ =3D 13, + IOPMP2_IRQ =3D 14, VIRTIO_IRQ =3D 1, /* 1 to 8 */ VIRTIO_COUNT =3D 8, PCIE_IRQ =3D 0x20, /* 32 to 35 */ --=20 2.34.1