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bh=orXRzHDIRCvpFIc7QJB2Jh5VhPPFE08CCclo6f2LkpY=; b=ieOvqQweZbWQ3LADwGSSrnlHzNnq52XGgQgCVHtCRbI5OtVho0xBVy9OkwVlQrn6qcEd/E hlx0CY6y5z/bzPuXFWpTx0qWN7FMhF0RNv94U4CwIDE+sao6sRQNGHYkqKivXxmFE2wD3K y2pHVjdBzbZxS6FOhy43hHWojhB7pGQ= X-MC-Unique: jg_08FfOMS-v5p9MzMgD8g-1 From: Jason Wang To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Akihiko Odaki , Sriram Yagnaraman , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 1/2] igb: Add a VF reset handler Date: Tue, 14 Nov 2023 11:09:36 +0800 Message-ID: <20231114030937.5461-2-jasowang@redhat.com> In-Reply-To: <20231114030937.5461-1-jasowang@redhat.com> References: <20231114030937.5461-1-jasowang@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1699931426700100001 From: C=C3=A9dric Le Goater Export the igb_vf_reset() helper routine from the PF model to let the IGBVF model implement its own device reset. Cc: Akihiko Odaki Suggested-by: Sriram Yagnaraman Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Jason Wang --- hw/net/igb.c | 6 ++++++ hw/net/igb_common.h | 1 + hw/net/igb_core.c | 6 ++++-- hw/net/igb_core.h | 3 +++ hw/net/igbvf.c | 10 ++++++++++ hw/net/trace-events | 1 + 6 files changed, 25 insertions(+), 2 deletions(-) diff --git a/hw/net/igb.c b/hw/net/igb.c index 8ff832a..e70a66e 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -122,6 +122,12 @@ igb_mmio_write(void *opaque, hwaddr addr, uint64_t val= , unsigned size) igb_core_write(&s->core, addr, val, size); } =20 +void igb_vf_reset(void *opaque, uint16_t vfn) +{ + IGBState *s =3D opaque; + igb_core_vf_reset(&s->core, vfn); +} + static bool igb_io_get_reg_index(IGBState *s, uint32_t *idx) { diff --git a/hw/net/igb_common.h b/hw/net/igb_common.h index 5c261ba..b316a5b 100644 --- a/hw/net/igb_common.h +++ b/hw/net/igb_common.h @@ -152,5 +152,6 @@ enum { =20 uint64_t igb_mmio_read(void *opaque, hwaddr addr, unsigned size); void igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size= ); +void igb_vf_reset(void *opaque, uint16_t vfn); =20 #endif diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index f6a5e23..2a7a11a 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -2477,11 +2477,13 @@ static void igb_set_vfmailbox(IGBCore *core, int in= dex, uint32_t val) } } =20 -static void igb_vf_reset(IGBCore *core, uint16_t vfn) +void igb_core_vf_reset(IGBCore *core, uint16_t vfn) { uint16_t qn0 =3D vfn; uint16_t qn1 =3D vfn + IGB_NUM_VM_POOLS; =20 + trace_igb_core_vf_reset(vfn); + /* disable Rx and Tx for the VF*/ core->mac[RXDCTL0 + (qn0 * 16)] &=3D ~E1000_RXDCTL_QUEUE_ENABLE; core->mac[RXDCTL0 + (qn1 * 16)] &=3D ~E1000_RXDCTL_QUEUE_ENABLE; @@ -2560,7 +2562,7 @@ static void igb_set_vtctrl(IGBCore *core, int index, = uint32_t val) =20 if (val & E1000_CTRL_RST) { vfn =3D (index - PVTCTRL0) / 0x40; - igb_vf_reset(core, vfn); + igb_core_vf_reset(core, vfn); } } =20 diff --git a/hw/net/igb_core.h b/hw/net/igb_core.h index 9cbbfd5..bf8c46f 100644 --- a/hw/net/igb_core.h +++ b/hw/net/igb_core.h @@ -130,6 +130,9 @@ igb_core_set_link_status(IGBCore *core); void igb_core_pci_uninit(IGBCore *core); =20 +void +igb_core_vf_reset(IGBCore *core, uint16_t vfn); + bool igb_can_receive(IGBCore *core); =20 diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index d55e1e8..07343fa 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -273,6 +273,13 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **= errp) pcie_ari_init(dev, 0x150); } =20 +static void igbvf_qdev_reset_hold(Object *obj) +{ + PCIDevice *vf =3D PCI_DEVICE(obj); + + igb_vf_reset(pcie_sriov_get_pf(vf), pcie_sriov_vf_number(vf)); +} + static void igbvf_pci_uninit(PCIDevice *dev) { IgbVfState *s =3D IGBVF(dev); @@ -287,6 +294,7 @@ static void igbvf_class_init(ObjectClass *class, void *= data) { DeviceClass *dc =3D DEVICE_CLASS(class); PCIDeviceClass *c =3D PCI_DEVICE_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); =20 c->realize =3D igbvf_pci_realize; c->exit =3D igbvf_pci_uninit; @@ -295,6 +303,8 @@ static void igbvf_class_init(ObjectClass *class, void *= data) c->revision =3D 1; c->class_id =3D PCI_CLASS_NETWORK_ETHERNET; =20 + rc->phases.hold =3D igbvf_qdev_reset_hold; + dc->desc =3D "Intel 82576 Virtual Function"; dc->user_creatable =3D false; =20 diff --git a/hw/net/trace-events b/hw/net/trace-events index 3097742..387e32e 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -274,6 +274,7 @@ igb_core_mdic_read(uint32_t addr, uint32_t data) "MDIC = READ: PHY[%u] =3D 0x%x" igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED" igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] =3D= 0x%x" igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLE= D" +igb_core_vf_reset(uint16_t vfn) "VF%d" =20 igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfr= std) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF = reset done: %d" =20 --=20 2.7.4 From nobody Wed Nov 27 07:36:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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bh=cAvT16XO+YxY7M6B/Ytiwt9SDHWAlr5QWhKe+kjfvuc=; b=X4xHSD/rKCQUCkFyPwsnKqo7OmyRWMreZ0Va3+E9SWtT/xXQuvuDN1K7sOBoWVFOOA7Udy uy59Z1mJUVXH82WYJBhmtCAS/SriD8eyEsA6PMOKx/D33moIDWofhYXyEKFzuaJH0qVjKz CgOL57kTzMBc9osFrqLQj2isIdsGXBc= X-MC-Unique: CbtqXFrtPxmKmQMKWpEUcw-1 From: Jason Wang To: qemu-devel@nongnu.org Cc: jasowang@redhat.com, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Sriram Yagnaraman , Akihiko Odaki Subject: [PULL 2/2] igb: Add Function Level Reset to PF and VF Date: Tue, 14 Nov 2023 11:09:37 +0800 Message-ID: <20231114030937.5461-3-jasowang@redhat.com> In-Reply-To: <20231114030937.5461-1-jasowang@redhat.com> References: <20231114030937.5461-1-jasowang@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1699931450604100005 From: C=C3=A9dric Le Goater The Intel 82576EB GbE Controller say that the Physical and Virtual Functions support Function Level Reset. Add the capability to the PF device model using device property "x-pcie-flr-init" which is "on" by default and "off" for machines <=3D 8.1 to preserve compatibility. The FLR capability of the VF model is defined according to the FLR property of the PF, this to avoid adding an extra compatibility property. Cc: Sriram Yagnaraman Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Jason Wang --- hw/core/machine.c | 3 ++- hw/net/igb.c | 9 +++++++++ hw/net/igbvf.c | 9 +++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 50edaab..0c17398 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -35,7 +35,8 @@ GlobalProperty hw_compat_8_1[] =3D { { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, { "ramfb", "x-migrate", "off" }, - { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" } + { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, + { "igb", "x-pcie-flr-init", "off" }, }; const size_t hw_compat_8_1_len =3D G_N_ELEMENTS(hw_compat_8_1); =20 diff --git a/hw/net/igb.c b/hw/net/igb.c index e70a66e..dfb722b 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -78,6 +78,7 @@ struct IGBState { uint32_t ioaddr; =20 IGBCore core; + bool has_flr; }; =20 #define IGB_CAP_SRIOV_OFFSET (0x160) @@ -101,6 +102,9 @@ static void igb_write_config(PCIDevice *dev, uint32_t a= ddr, =20 trace_igb_write_config(addr, val, len); pci_default_write_config(dev, addr, val, len); + if (s->has_flr) { + pcie_cap_flr_write_config(dev, addr, val, len); + } =20 if (range_covers_byte(addr, len, PCI_COMMAND) && (dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { @@ -433,6 +437,10 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error = **errp) } =20 /* PCIe extended capabilities (in order) */ + if (s->has_flr) { + pcie_cap_flr_init(pci_dev); + } + if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) { hw_error("Failed to initialize AER capability"); } @@ -588,6 +596,7 @@ static const VMStateDescription igb_vmstate =3D { =20 static Property igb_properties[] =3D { DEFINE_NIC_PROPERTIES(IGBState, conf), + DEFINE_PROP_BOOL("x-pcie-flr-init", IGBState, has_flr, true), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c index 07343fa..94a4e88 100644 --- a/hw/net/igbvf.c +++ b/hw/net/igbvf.c @@ -204,6 +204,10 @@ static void igbvf_write_config(PCIDevice *dev, uint32_= t addr, uint32_t val, { trace_igbvf_write_config(addr, val, len); pci_default_write_config(dev, addr, val, len); + if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)), + "x-pcie-flr-init", &error_abort)) { + pcie_cap_flr_write_config(dev, addr, val, len); + } } =20 static uint64_t igbvf_mmio_read(void *opaque, hwaddr addr, unsigned size) @@ -266,6 +270,11 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **= errp) hw_error("Failed to initialize PCIe capability"); } =20 + if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)), + "x-pcie-flr-init", &error_abort)) { + pcie_cap_flr_init(dev); + } + if (pcie_aer_init(dev, 1, 0x100, 0x40, errp) < 0) { hw_error("Failed to initialize AER capability"); } --=20 2.7.4