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([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911573; x=1700516373; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qCqMpypxYhR2XXGBnvs8P3AJK9PzGYu4JOrjRZN4juc=; b=fBfKMuNq8Ygs1B/WyhGOlKdtIkXW78A55rSUmtdZStyOTjDId7Obp8rWGw793gX7On 1lNJRh3V+Wgr5YnU+b+O6KZYKFphWWrSSKGEm5geX7k/NLrSexAQMQria0DnUScsIrSo K7jNwepddeo5CcgZTbVTSRkPZJxiT5FC97lEQk96FY9gFD4t75Dja3z2bJhYIwAD9ATu lT33/7J3JusAZKcJlWv77odlw7nRgb2L2mn3ZacDzo3EUEu4bFJCvo8kEHMmnDLBfxaz WQqDahrLlbjHO8Iq+sMHL3TKab0y/juoaXC4/aEbN/6FO+SDE5ga0Lk3Epqm5mM0uMkZ 1leQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911573; x=1700516373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qCqMpypxYhR2XXGBnvs8P3AJK9PzGYu4JOrjRZN4juc=; b=uTyxkqILwK+cVnf0bVmFYTHJJc2aR6TYw1D93l6i/1mu1gV5lvb7jm0eo4ZbjHs5+8 I5ldxk5bwbegzfcnmdWYTT/E9cpxZ302I5WdWP07+kGkRABQzhPYbWOv++YR5frEGSFp ISsldylaZ6fZl6xYUTs82iK8NK7tpX6qQqPNVskQUezVOnqoQenwQqpuvmh3Ssz5EiHc TWpcXja3M2bRcM6Vfx0xx0vAQLrDzSqx86KtZlglIrqIB3EEwpnN6fnb3NFwcwmT+oRJ qFjdErmaLKemHydabTUZj77u9EkM1BcS367XmCRe/NSJr6vOCd9z7rgI8qRm6+3k7adi BEfw== X-Gm-Message-State: AOJu0YygLP71Kx45hmzdxDBHjWAMqVw8cHBt1c01D2+QkMifSsbmQTp0 gNkOfaTah7ub4dePAeo4u0eQSUjX7y8ulQL6lig= X-Google-Smtp-Source: AGHT+IF0+LzM7AX6PcgIaK3amHGT48pREfAOCC4/uo37bCL4/jYadOX0xdYrkS5n5ZQBDBDMV5+iVg== X-Received: by 2002:a17:902:db07:b0:1cc:5dd4:7ce5 with SMTP id m7-20020a170902db0700b001cc5dd47ce5mr648135plx.19.1699911573238; Mon, 13 Nov 2023 13:39:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 6/6] target/riscv: add rv32e/rv64e CPUs Date: Mon, 13 Nov 2023 18:39:04 -0300 Message-ID: <20231113213904.185320-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911616773100005 Content-Type: text/plain; charset="utf-8" In our internals we'll never allow RVI and RVE to be enabled at the same time, and we require either RVI or RVE to be enabled to proceed with machine boot. And all CPUs we have enables RVI by default. This means that if one wants to create an embedded CPU he'll need to disable RVI first then enable RVE, e.g.: -cpu rv64i,i=3Dfalse,e=3Dtrue Let's add two RVE CPUs to ease the burder when working with embedded CPUs in QEMU. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index f345c17e69..34d1034cfc 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -36,6 +36,8 @@ #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") +#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e") +#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55cf114b61..7d5ff7a0aa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -585,6 +585,28 @@ static void rv64i_bare_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); #endif } + +static void rv64e_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV64, RVE); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); +#endif +} #else static void rv32_base_cpu_init(Object *obj) { @@ -688,6 +710,28 @@ static void rv32i_bare_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif } + +static void rv32e_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV32, RVE); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -1883,6 +1927,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, rv32e_bare_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), @@ -1892,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, rv64e_bare_cpu_init), #endif }; =20 --=20 2.41.0