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([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911562; x=1700516362; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jmMujTAnDCnLNQCIKB7A1R2XebVoD2eMHYsCnu9fyhk=; b=O02OGq8InUtk1FbDVI1FCuiIhoDCO+IM0SWZ2vAjkBfstSYR05O8EDcJgMubSU2R29 Of40NHhI9Ev2S8eWcT16kEal8aA9H4rZ4/PT/I++oAPpd08BtCG/ik6gvGpm033xkJVk 60LN+ggXV+yNkj7L+LUPmiTUDuy83pCvBaUZk1CgcQi/bxSDuzjqXfeQTeg1gNSEQzki u9ZvZP1P2RFajh9K+ieGjWh6VnGrk4DOulFswchO+9VTdL1R3MWbcf8d4lLlASk7fHAk 7O84cNGAgXK//oXKnvdUvyXToG4NrL/bhjaJnDPAJKchbuntPlBps1FV3K/+hQMvPTmU tcRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911562; x=1700516362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jmMujTAnDCnLNQCIKB7A1R2XebVoD2eMHYsCnu9fyhk=; b=giZY76XvecD4hJQx7RCxjJOIMz4EmBM7v+cFivq7aYlJIhrJuxD+pXr2/yCZIW+ZO3 nvEndsTRnI4RXX/g88Rjux17lxm76hs1Pqm1fxL3Zait/WDTSY5Vsp5yA8B0z2L8eOb1 zK50mRIKustJ5y1N4ye1O/8wHyL4lZTVs065Q7qFfGnv/4AnmolE74xia2mlDXIth3Sq aRZG+CruRuS6d9KBBaF8XKdR+9qhAEp4SVCKLHySvSIFyu3+CyglClqrhe7CEOIgLNUD 09n0hs3QlLKrokaw26BYMB+6REKAf3LIy3J+gp574FjUnDUctWicS/bFqFsxLqiIQgTf nkvA== X-Gm-Message-State: AOJu0YzwetPOB1DSWNau7+rw7cTwV1rrga8+huYltABkcbnqxjDfXEm7 cbGumBoB+4QTv+2swN7lj3DQBKw52qcD4axjG20= X-Google-Smtp-Source: AGHT+IFtumLXoXJHE5GgejqeRFnAxZ34EQZzDRBdIuMBq+5FIfAHHtsEfIaCBgZ9t/Od0Z1n5CA+0A== X-Received: by 2002:a17:902:a403:b0:1c9:aac5:df30 with SMTP id p3-20020a170902a40300b001c9aac5df30mr419352plq.66.1699911561886; Mon, 13 Nov 2023 13:39:21 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH for-9.0 2/6] target/riscv/tcg: do not use "!generic" CPU checks Date: Mon, 13 Nov 2023 18:39:00 -0300 Message-ID: <20231113213904.185320-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911678934100001 Content-Type: text/plain; charset="utf-8" Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu inste= ad of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 08adad304d..304211169e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -654,6 +654,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -722,7 +727,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -736,7 +741,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, } =20 if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -841,7 +846,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -865,7 +870,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); --=20 2.41.0