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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id a11-20020a170906190b00b0098d2d219649sm3807321eje.174.2023.11.13.01.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 01:56:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1699869371; x=1700474171; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iB7fJ0gWQ/iabhlhIhHFNNkXK5uKgJMYdkpTFw7eBpY=; b=clLCLodta6XvbP7pxBR8+o9oIuDkrEHHHSRYGyyz/j6rqYIR8ipdR3jhDeDh66XaIL Rpr5jRW0KwsmO2w8H4tFAVwFwDszokrviz2rjkDlpl84Va+njokWtuDaF4MzoS+f2XWC PFkg1s3MYCMMpk/JrCZZDTrYHQi+0eiTUPDSIkAFIWd9ezVbrwyiCpG/wN9sHGjUVc5M 6rDyLN1ekKufC1nuX8GwTD5ngiWHHjWGvNYcTeTxSg3Kj9gP7gi+ZLa1Vg+CA5/3K148 xaFy85BPk1sEevJ3I7pUAuRRB61908lD6f0Jcf7g7rQFTSxJA8VfYyfS0IuyF1nTLy/i /9rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699869371; x=1700474171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iB7fJ0gWQ/iabhlhIhHFNNkXK5uKgJMYdkpTFw7eBpY=; b=ikdPzuvZqdG1S4i+lc4RFhjciXLbbbTA94/Rd+78stKMq5+aXuZVtnDboVgqiOAYUu rkIN46Yu91pFw6QOGlyhGF2r8pwvigv7HOp9rG3ukv9/MZfkYXEgYvSXmbm7e7rQHf3O Z5+/wDPJ64l6kjUxPIAXdqsh/njnnADmCSYI7pVg4md/RaVh+6Fc59xJhfh/xUN5An8U C6g7l6CWNNpO1sUaTvTKquXu6DOMY5sOzv/9pfK1XCiwr9yXgnC6ZIDZeygq719vRPBU 4v7qKkwDoTPuQOsP/jOHYthP0aU0mUX+7OX0zxj2NedXaUQROomM7Psq49bIvcWLiery +IIg== X-Gm-Message-State: AOJu0YxoTHbNUJg/oqtqQjPh5PGDHFpBf2vjJNg7srTzUMEW8TbIC43w Tob3mViiRWJZESS3uLdLAfEq5QKGBNO9G7MfaVw= X-Google-Smtp-Source: AGHT+IGwwfO967eP37t2S+yYCQilcSkds0fv7zRJGCtrvHbt96K1FadWFwm237h6m0aNFkmI6RDV7g== X-Received: by 2002:a17:906:7754:b0:9db:9c5e:a9c5 with SMTP id o20-20020a170906775400b009db9c5ea9c5mr3971106ejn.33.1699869370748; Mon, 13 Nov 2023 01:56:10 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson Cc: Palmer Dabbelt , =?UTF-8?q?Christoph=20M=C3=BCllner?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [RFC PATCH 1/2] RISC-V: Add support for Ztso Date: Mon, 13 Nov 2023 10:56:02 +0100 Message-ID: <20231113095605.1131443-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113095605.1131443-1-christoph.muellner@vrull.eu> References: <20231113095605.1131443-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1699869470045100001 From: Palmer Dabbelt The Ztso extension is already ratified, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs as they're already SC, the placess we need barriers are described. These fences are placed in the RISC-V backend rather than TCG as is planned for x86-on-arm64 because RISC-V allows heterogenous (and likely soon dynamic) hart memory models. Signed-off-by: Palmer Dabbelt Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++--- target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++-- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++ target/riscv/translate.c | 3 +++ 6 files changed, 48 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07..b446e553b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso), ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), @@ -1336,6 +1337,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), + MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false), =20 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..a0f951d9c1 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -70,6 +70,7 @@ struct RISCVCPUConfig { bool ext_zihintntl; bool ext_zihintpause; bool ext_zihpm; + bool ext_ztso; bool ext_smstateen; bool ext_sstc; bool ext_svadu; diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 5f194a447b..85c7e31f2a 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -28,7 +28,11 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Mem= Op mop) tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); - if (a->aq) { + /* + * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC= as + * AMOs. Instead treat them like loads. + */ + if (a->aq || ctx->ztso) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } =20 @@ -64,9 +68,10 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Mem= Op mop) gen_set_label(l1); /* * Address comparison failure. However, we still need to - * provide the memory barrier implied by AQ/RL. + * provide the memory barrier implied by AQ/RL/TSO. */ - tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); + TCGBar bar_strl =3D (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0; + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl); gen_set_gpr(ctx, a->rd, tcg_constant_tl(1)); =20 gen_set_label(l2); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index faf6d65064..ad40d3e87f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -266,12 +266,20 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *= a, MemOp memop) =20 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { + bool out; + decode_save_opc(ctx); if (get_xl(ctx) =3D=3D MXL_RV128) { - return gen_load_i128(ctx, a, memop); + out =3D gen_load_i128(ctx, a, memop); } else { - return gen_load_tl(ctx, a, memop); + out =3D gen_load_tl(ctx, a, memop); + } + + if (ctx->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } + + return out; } =20 static bool trans_lb(DisasContext *ctx, arg_lb *a) @@ -328,6 +336,10 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a,= MemOp memop) TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 + if (ctx->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 78bd363310..76e63fcbca 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -636,8 +636,28 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, u= int32_t data, tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 + /* + * According to the specification + * + * Additionally, if the Ztso extension is implemented, then vector m= emory + * instructions in the V extension and Zve family of extensions foll= ow + * RVTSO at the instruction level. The Ztso extension does not + * strengthen the ordering of intra-instruction element accesses. + * + * as a result neither ordered nor unordered accesses from the V + * instructions need ordering within the loop but we do still need bar= riers + * around the loop. + */ + if (is_store && s->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + fn(dest, mask, base, tcg_env, desc); =20 + if (!is_store && s->ztso) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + if (!is_store) { mark_vs_dirty(s); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..ab56051d6d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -109,6 +109,8 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; + /* Ztso */ + bool ztso; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1194,6 +1196,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); + ctx->ztso =3D cpu->cfg.ext_ztso; ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; --=20 2.41.0