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Fri, 10 Nov 2023 17:32:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 08/11] target/hppa: Introduce MMU_IDX_MMU_DISABLED Date: Fri, 10 Nov 2023 17:32:09 -0800 Message-Id: <20231111013212.229673-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231111013212.229673-1-richard.henderson@linaro.org> References: <20231111013212.229673-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699666437105100005 Content-Type: text/plain; charset="utf-8" Reduce the number of direct checks against MMU_PHYS_IDX. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 4 ++-- target/hppa/translate.c | 20 +++++++++++--------- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index cecec59700..6c0f104661 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -41,6 +41,7 @@ #define MMU_USER_P_IDX 14 #define MMU_PHYS_IDX 15 =20 +#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) =3D=3D MMU_PHYS_IDX) #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a13f200359..af8e86699d 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -367,8 +367,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx); =20 /* Failure. Raise the indicated exception. */ - raise_exception_with_ior(env, excp, retaddr, - addr, mmu_idx =3D=3D MMU_PHYS_IDX); + raise_exception_with_ior(env, excp, retaddr, addr, + MMU_IDX_MMU_DISABLED(mmu_idx)); } =20 trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bb1b65fef0..727dd8a829 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -69,9 +69,11 @@ typedef struct DisasContext { } DisasContext; =20 #ifdef CONFIG_USER_ONLY -#define UNALIGN(C) (C)->unalign +#define UNALIGN(C) (C)->unalign +#define MMU_DISABLED(C) false #else -#define UNALIGN(C) MO_ALIGN +#define UNALIGN(C) MO_ALIGN +#define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx) #endif =20 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ @@ -1375,7 +1377,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); @@ -1393,7 +1395,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); @@ -1411,7 +1413,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); @@ -1429,7 +1431,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); @@ -3078,7 +3080,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) } =20 form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, - a->disp, a->sp, a->m, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + a->disp, a->sp, a->m, MMU_DISABLED(ctx)); =20 /* * For hppa1.1, LDCW is undefined unless aligned mod 16. @@ -3108,7 +3110,7 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a) nullify_over(ctx); =20 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); val =3D load_gpr(ctx, a->r); if (a->a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { @@ -3142,7 +3144,7 @@ static bool trans_stdby(DisasContext *ctx, arg_stby *= a) nullify_over(ctx); =20 form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, - ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + MMU_DISABLED(ctx)); val =3D load_gpr(ctx, a->r); if (a->a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { --=20 2.34.1