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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699666408991100001 Content-Type: text/plain; charset="utf-8" From: Helge Deller Apply the "32-bit PCI addressing on 40-bit Runway" as the default iommu transformation. This allows PCI devices to dma PDC memory. Signed-off-by: Helge Deller Acked-by: Richard Henderson Signed-off-by: Richard Henderson --- hw/pci-host/astro.c | 73 ++++++++++++++++++----------------------- hw/pci-host/meson.build | 2 +- 2 files changed, 33 insertions(+), 42 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index bd226581af..7d68ccee7e 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -32,6 +32,7 @@ #include "hw/pci-host/astro.h" #include "hw/hppa/hppa_hardware.h" #include "migration/vmstate.h" +#include "target/hppa/cpu.h" #include "trace.h" #include "qom/object.h" =20 @@ -268,22 +269,6 @@ static const MemoryRegionOps elroy_config_addr_ops =3D= { }; =20 =20 -/* - * A subroutine of astro_translate_iommu that builds an IOMMUTLBEntry usin= g the - * given translated address and mask. - */ -static bool make_iommu_tlbe(hwaddr addr, hwaddr taddr, hwaddr mask, - IOMMUTLBEntry *ret) -{ - hwaddr tce_mask =3D ~((1ull << 12) - 1); - ret->target_as =3D &address_space_memory; - ret->iova =3D addr & tce_mask; - ret->translated_addr =3D taddr & tce_mask; - ret->addr_mask =3D ~tce_mask; - ret->perm =3D IOMMU_RW; - return true; -} - /* Handle PCI-to-system address translation. */ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, @@ -291,53 +276,59 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemor= yRegion *iommu, int iommu_idx) { AstroState *s =3D container_of(iommu, AstroState, iommu); - IOMMUTLBEntry ret =3D { - .target_as =3D &address_space_memory, - .iova =3D addr, - .translated_addr =3D 0, - .addr_mask =3D ~(hwaddr)0, - .perm =3D IOMMU_NONE, - }; - hwaddr pdir_ptr, index, a, ibase; + hwaddr pdir_ptr, index, ibase; hwaddr addr_mask =3D 0xfff; /* 4k translation */ uint64_t entry; =20 #define IOVP_SHIFT 12 /* equals PAGE_SHIFT */ #define PDIR_INDEX(iovp) ((iovp) >> IOVP_SHIFT) -#define IOVP_MASK PAGE_MASK #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL =20 + addr &=3D ~addr_mask; + + /* + * Default translation: "32-bit PCI Addressing on 40-bit Runway". + * For addresses in the 32-bit memory address range ... and then + * language which not-coincidentally matches the PSW.W=3D0 mapping. + */ + if (addr <=3D UINT32_MAX) { + entry =3D hppa_abs_to_phys_pa2_w0(addr); + } else { + entry =3D addr; + } + /* "range enable" flag cleared? */ if ((s->tlb_ibase & 1) =3D=3D 0) { - make_iommu_tlbe(addr, addr, addr_mask, &ret); - return ret; + goto skip; } =20 - a =3D addr; ibase =3D s->tlb_ibase & ~1ULL; - if ((a & s->tlb_imask) !=3D ibase) { + if ((addr & s->tlb_imask) !=3D ibase) { /* do not translate this one! */ - make_iommu_tlbe(addr, addr, addr_mask, &ret); - return ret; + goto skip; } - index =3D PDIR_INDEX(a); + + index =3D PDIR_INDEX(addr); pdir_ptr =3D s->tlb_pdir_base + index * sizeof(entry); entry =3D ldq_le_phys(&address_space_memory, pdir_ptr); + if (!(entry & SBA_PDIR_VALID_BIT)) { /* I/O PDIR entry valid ? */ - g_assert_not_reached(); - goto failure; + /* failure */ + return (IOMMUTLBEntry) { .perm =3D IOMMU_NONE }; } + entry &=3D ~SBA_PDIR_VALID_BIT; entry >>=3D IOVP_SHIFT; entry <<=3D 12; - entry |=3D addr & 0xfff; - make_iommu_tlbe(addr, entry, addr_mask, &ret); - goto success; =20 - failure: - ret =3D (IOMMUTLBEntry) { .perm =3D IOMMU_NONE }; - success: - return ret; + skip: + return (IOMMUTLBEntry) { + .target_as =3D &address_space_memory, + .iova =3D addr, + .translated_addr =3D entry, + .addr_mask =3D addr_mask, + .perm =3D IOMMU_RW, + }; } =20 static AddressSpace *elroy_pcihost_set_iommu(PCIBus *bus, void *opaque, diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index de7bfb5a62..36d5ab756f 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -29,7 +29,7 @@ pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv6436= 1.c')) pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c')) =20 # HPPA devices -pci_ss.add(when: 'CONFIG_ASTRO', if_true: files('astro.c')) +specific_ss.add(when: 'CONFIG_ASTRO', if_true: files('astro.c')) pci_ss.add(when: 'CONFIG_DINO', if_true: files('dino.c')) =20 system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) --=20 2.34.1