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Fri, 10 Nov 2023 17:32:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 10/11] target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 44 Date: Fri, 10 Nov 2023 17:32:11 -0800 Message-Id: <20231111013212.229673-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231111013212.229673-1-richard.henderson@linaro.org> References: <20231111013212.229673-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699666465184100003 Content-Type: text/plain; charset="utf-8" This is the maximum that was ever supported, in the PA-8700 thru PA-8900. If we support a larger address space than expected, we trip up software that did not fill in all of the page table bits, expecting them to be ignored. Signed-off-by: Richard Henderson --- target/hppa/cpu-param.h | 2 +- target/hppa/mem_helper.c | 50 ++++++++++++++++++++++++++-------------- 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 6746869a3b..7a8b216133 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -14,7 +14,7 @@ # define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -# define TARGET_PHYS_ADDR_SPACE_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 44 # define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 7bc456d4ee..08abd1a9f9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -27,30 +27,39 @@ =20 hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) { - if (likely(extract64(addr, 58, 4) !=3D 0xf)) { - /* Memory address space */ - return addr & MAKE_64BIT_MASK(0, 62); - } - if (extract64(addr, 54, 4) !=3D 0) { - /* I/O address space */ - return addr | MAKE_64BIT_MASK(62, 2); - } - /* PDC address space */ - return (addr & MAKE_64BIT_MASK(0, 54)) | MAKE_64BIT_MASK(60, 4); + /* + * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes + * an algorithm in which a 62-bit absolute address is transformed to + * a 64-bit physical address. This must then be combined with that + * pictured in Figure H-11 "Physical Address Space Mapping", in which + * the full physical address is truncated to the N-bit physical address + * supported by the implementation. + * + * Since the supported physical address space is below 54 bits, the + * H-8 algorithm is moot and all that is left is to truncate. + */ + QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 54); + return sextract64(addr, 0, TARGET_PHYS_ADDR_SPACE_BITS); } =20 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) { + /* + * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", + * combined with Figure H-11, as above. + */ if (likely(extract32(addr, 28, 4) !=3D 0xf)) { /* Memory address space */ - return addr & MAKE_64BIT_MASK(0, 32); - } - if (extract32(addr, 24, 4) !=3D 0) { + addr =3D (uint32_t)addr; + } else if (extract32(addr, 24, 4) !=3D 0) { /* I/O address space */ - return addr | MAKE_64BIT_MASK(32, 32); + addr =3D (int32_t)addr; + } else { + /* PDC address space */ + addr &=3D MAKE_64BIT_MASK(0, 24); + addr |=3D -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4); } - /* PDC address space */ - return (addr & MAKE_64BIT_MASK(0, 24)) | MAKE_64BIT_MASK(60, 4); + return addr; } =20 static HPPATLBEntry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) @@ -460,7 +469,14 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong= r1, =20 ent->itree.start =3D va_b; ent->itree.last =3D va_e; - ent->pa =3D (r1 << 7) & (TARGET_PAGE_MASK << mask_shift); + + /* Extract all 52 bits present in the page table entry. */ + ent->pa =3D r1 << (TARGET_PAGE_BITS - 5); + /* Align per the page size. */ + ent->pa &=3D TARGET_PAGE_MASK << mask_shift; + /* Ignore the bits beyond physical address space. */ + ent->pa =3D sextract64(ent->pa, 0, TARGET_PHYS_ADDR_SPACE_BITS); + ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); ent->b =3D extract64(r2, 59, 1); --=20 2.34.1