From nobody Wed Nov 27 12:37:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1699390239; cv=none; d=zohomail.com; s=zohoarc; b=WAY0sZYEMDb3pWd5nRgEdDSGRxrTjW5OqV+V/c6fExIBuvERwvXvwLPzXCkuZi2EBkpPCI8ZP3k7WWWLP+AgCsnn3Y5FBxyVQuOCVppDzY0CVxvhgQeV3x5yENpyypJHXDb5Yggaths8c2U3SQVdahhM5eCey+5CVpgf/+qG8eE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699390239; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AuiB8YLB6fW19Sv4iIZuZRWwFlQIhnLJeadaVGwfrms=; b=apVKDsRn23K+lX+eIzPpOUnlQhMqwFSdJstNJGeIYhrX/pbpBUR+YR4A+ML16aOus+964B0wtt8Fu4ZimOR9ZLg8kwAmG6fG3Lw6mDHwipzVHFBWaW5aZv8USblRiwek44Z1RglG8OK5HnO8OxBDpVDrOMmcl0Wl9xDbEBqSPB0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699390239234957.0583184152914; Tue, 7 Nov 2023 12:50:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0Szu-0006aS-1w; Tue, 07 Nov 2023 15:48:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0Szr-0006YE-TK; Tue, 07 Nov 2023 15:48:27 -0500 Received: from mail-qt1-x830.google.com ([2607:f8b0:4864:20::830]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r0Szq-0006SM-5e; Tue, 07 Nov 2023 15:48:27 -0500 Received: by mail-qt1-x830.google.com with SMTP id d75a77b69052e-41cd6e1d4fbso36742141cf.1; Tue, 07 Nov 2023 12:48:25 -0800 (PST) Received: from grind.. ([179.193.10.161]) by smtp.gmail.com with ESMTPSA id d13-20020ac8544d000000b0041eb13a8195sm48946qtq.61.2023.11.07.12.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 12:48:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699390104; x=1699994904; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AuiB8YLB6fW19Sv4iIZuZRWwFlQIhnLJeadaVGwfrms=; b=DYYYcgIPLVJbzJhbsn6tUq0UAn2z5rKAadcdNzB1FHOVPIfXJLJeBtpLCyO3pqobsg L4oP/s6qFzzABoO2egeFrMO9UYaUu2OB6SbrcBZfoxtdoH+CmBjjMbQt1xJQFQO3M/B0 MFSsnh1aScKCfQ0iSZ7YORGIInJ30Ev0nq+oPhBoCy5q8uBCQJ4T5lPS/jNuke209u55 bs9MmabZb/G6nR53tlwBvNUOog6yTW4O3IUSiUkwApYh4kA+xXt9dYBm8gXq39cFE2L4 csYuWklbZrUBciQHiB+8NsfNnapT4sxMiz11s7t2Mhv/rRymdf7OQuaNJrKjO49zPPDz Bl0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699390104; x=1699994904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AuiB8YLB6fW19Sv4iIZuZRWwFlQIhnLJeadaVGwfrms=; b=sr71KsXQ+xq6V4ewJtqIF/fkC2nMhhHe19M/lo7WhbecqdiwMKkBneT4IYIPClOjBI eD71HAw3n6oW/kkj8B4fp30iGKG6FAdU1DF/Kf5gEgQHThrOIjCdW77uXQcSyRNyKQ5Q F6L9CDyDdqzN+T6r6CDyScZpfsqyBTJ4i4jj+7UV7n+tloqXdal429HYQBRAwUIHjPAd aeP90ADudvz6+y43DeAz/CieTRGglHju91kntFFICVlVst7K6Czy6GTCCAyIHzDtocDV l8wj3OfGnb/sxMLVStf/jVXtB+sEPYgYeef4P+e4WV16cXnIXdti70Ln4yv9d7d1JXPz AZDQ== X-Gm-Message-State: AOJu0YxXEvdA7N9QN9FzIr+waMaUCI7iaIdMEcNS9FMfHjEpFwUUe4zn 9UPisEyFHGH/8e7E+OoRf00YBPoGyaI= X-Google-Smtp-Source: AGHT+IHmwHIWejHpTz+YaRHBguR/1xfLwspLpuT7RAgmXOxj7ynshxOtYUCKVsUDKwGtHYWnNjv+jg== X-Received: by 2002:a05:622a:1b8e:b0:41c:c2ad:6810 with SMTP id bp14-20020a05622a1b8e00b0041cc2ad6810mr1584qtb.2.1699390104464; Tue, 07 Nov 2023 12:48:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, Glenn Miles , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 7/9] ppc/pnv: Fix number of I2C engines and ports for power9/10 Date: Tue, 7 Nov 2023 17:48:04 -0300 Message-ID: <20231107204806.8507-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107204806.8507-1-danielhb413@gmail.com> References: <20231107204806.8507-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x830.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699390241347100003 From: Glenn Miles Power9 is supposed to have 4 PIB-connected I2C engines with the following number of ports on each engine: 0: 2 1: 13 2: 2 3: 2 Power10 also has 4 engines but has the following number of ports on each engine: 0: 14 1: 14 2: 2 3: 16 Current code assumes that they all have the same (maximum) number. This can be a problem if software expects to see a certain number of ports present (Power Hypervisor seems to care). Fixed this by adding separate tables for power9 and power10 that map the I2C controller number to the number of I2C buses that should be attached for that engine. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Glenn Miles Message-ID: <20231025152714.956664-1-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/pnv.c | 12 ++++++++---- include/hw/ppc/pnv_chip.h | 6 ++---- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ae8e0b45cd..9c29727337 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1615,7 +1615,8 @@ static void pnv_chip_power9_realize(DeviceState *dev,= Error **errp) Object *obj =3D OBJECT(&chip9->i2c[i]); =20 object_property_set_int(obj, "engine", i + 1, &error_fatal); - object_property_set_int(obj, "num-busses", pcc->i2c_num_ports, + object_property_set_int(obj, "num-busses", + pcc->i2c_ports_per_engine[i], &error_fatal); object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); if (!qdev_realize(DEVICE(obj), NULL, errp)) { @@ -1640,6 +1641,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] =3D {2, 13, 2= , 2}; =20 k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; @@ -1656,7 +1658,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) dc->desc =3D "PowerNV Chip POWER9"; k->num_pecs =3D PNV9_CHIP_MAX_PEC; k->i2c_num_engines =3D PNV9_CHIP_MAX_I2C; - k->i2c_num_ports =3D PNV9_CHIP_MAX_I2C_PORTS; + k->i2c_ports_per_engine =3D i2c_ports_per_engine; =20 device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); @@ -1861,7 +1863,8 @@ static void pnv_chip_power10_realize(DeviceState *dev= , Error **errp) Object *obj =3D OBJECT(&chip10->i2c[i]); =20 object_property_set_int(obj, "engine", i + 1, &error_fatal); - object_property_set_int(obj, "num-busses", pcc->i2c_num_ports, + object_property_set_int(obj, "num-busses", + pcc->i2c_ports_per_engine[i], &error_fatal); object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); if (!qdev_realize(DEVICE(obj), NULL, errp)) { @@ -1886,6 +1889,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] =3D {14, 14,= 2, 16}; =20 k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask =3D POWER10_CORE_MASK; @@ -1902,7 +1906,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) dc->desc =3D "PowerNV Chip POWER10"; k->num_pecs =3D PNV10_CHIP_MAX_PEC; k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C; - k->i2c_num_ports =3D PNV10_CHIP_MAX_I2C_PORTS; + k->i2c_ports_per_engine =3D i2c_ports_per_engine; =20 device_class_set_parent_realize(dc, pnv_chip_power10_realize, &k->parent_realize); diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 5815d96ecf..0ab5c42308 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -88,8 +88,7 @@ struct Pnv9Chip { #define PNV9_CHIP_MAX_PEC 3 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; =20 -#define PNV9_CHIP_MAX_I2C 3 -#define PNV9_CHIP_MAX_I2C_PORTS 1 +#define PNV9_CHIP_MAX_I2C 4 PnvI2C i2c[PNV9_CHIP_MAX_I2C]; }; =20 @@ -122,7 +121,6 @@ struct Pnv10Chip { PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; =20 #define PNV10_CHIP_MAX_I2C 4 -#define PNV10_CHIP_MAX_I2C_PORTS 2 PnvI2C i2c[PNV10_CHIP_MAX_I2C]; }; =20 @@ -140,7 +138,7 @@ struct PnvChipClass { uint32_t num_phbs; =20 uint32_t i2c_num_engines; - uint32_t i2c_num_ports; + const int *i2c_ports_per_engine; =20 DeviceRealize parent_realize; =20 --=20 2.41.0