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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id d13-20020ac8544d000000b0041eb13a8195sm48946qtq.61.2023.11.07.12.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 12:48:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699390093; x=1699994893; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UxOhMl2wqsbZK7xoOekGJBbt7dObwp6VMHmgjJubr/E=; b=YLvvRSHchn9Q4SurkGsg3zb4jy++rVUUjj/FhAKuiu8jWXnkRAFDhDL2hr8p7OgPeK ZCER0K9N7F69rzxBQMVA1VNxHT8pWj1LP65bJEOt6yDI3LAjD03bvleWPzMvLh4zF548 HgLrgh9FJnMH4doHSB1SQFOVdpYeFwJ0Nh4hHWou3ng9+y9WcXyjgI1Px76Jk638K4W9 UtlaElwKN4rZ5sSrZyeLuOH3aHqIWbZrv4cgh2oQ/BwTsPiOhB5ATtiiQbjPeMu7aEHH 7ZKC5ZG5Skl8nk69GJBEvS49xLacNmq7GqJxHJAQWgQxsCNWipj1+fL8TRuhbWgZTAP7 03bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699390093; x=1699994893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UxOhMl2wqsbZK7xoOekGJBbt7dObwp6VMHmgjJubr/E=; b=TvSlCCSWycNUua+6fLXcwKv5OuwoQApVCTChHlQg0dA4d9Tqnpl+U2iIWOssDHYIEJ pwAmAycES1uDBCVVVfxYPfaISMms0cWPnDrp6VHSKZDo0vdcFwfyUXU4o1/Lon2BrTKU wxw3V8N0XWqmjcjm2HrdJEjCFRBYe1imKr0SPjTyoC2BgT/Ai0u3Pt1B50kJWnMlU3cu npAcgdOiY9CMp4JkqIgGeMQJagmxqS7pHFdBl9D6DSRgAQDLopQqkqISon73cJBtaFoq mrA7BhBwjH9Ilwszt2fFh86OVutsvADeaEec5C7Lhj0eLnipSMhpi80CUTEErJo5n8oI 16rQ== X-Gm-Message-State: AOJu0Yz75Z7uc/I585YcZ4GdVOcaBRoVFtyhTXM9g38ku0BvelWteTbi l/zSNABhtm2CuAn4ZZZfAV7wK/prltc= X-Google-Smtp-Source: AGHT+IFk+6KchhUacaY7DK9Lq6DMZrLg8y7yU86Sn3fyPYHbgyW+j9/cch1yVQYL3iDazIHoNjMMoA== X-Received: by 2002:a05:6830:917:b0:6c4:9fda:a1e2 with SMTP id v23-20020a056830091700b006c49fdaa1e2mr33084162ott.4.1699390092857; Tue, 07 Nov 2023 12:48:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, BALATON Zoltan , Rene Engel Subject: [PULL 1/9] hw/pci-host: Add emulation of Mai Logic Articia S Date: Tue, 7 Nov 2023 17:47:58 -0300 Message-ID: <20231107204806.8507-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107204806.8507-1-danielhb413@gmail.com> References: <20231107204806.8507-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699390161378100007 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan The Articia S is a generic chipset supporting several different CPUs that were among others used on some PPC boards. This is a minimal emulation of the parts needed for emulating the AmigaOne board. Signed-off-by: BALATON Zoltan Tested-by: Rene Engel Acked-by: Daniel Henrique Barboza Message-ID: <83822787431701cf4d460298d3e3845f362e5da1.1698406922.git.balato= n@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/Kconfig | 5 + hw/pci-host/articia.c | 293 ++++++++++++++++++++++++++++++++++ hw/pci-host/meson.build | 2 + include/hw/pci-host/articia.h | 17 ++ 4 files changed, 317 insertions(+) create mode 100644 hw/pci-host/articia.c create mode 100644 include/hw/pci-host/articia.h diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 54a609d2ca..f046d76a68 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -73,6 +73,11 @@ config SH_PCI bool select PCI =20 +config ARTICIA + bool + select PCI + select I8259 + config MV64361 bool select PCI diff --git a/hw/pci-host/articia.c b/hw/pci-host/articia.c new file mode 100644 index 0000000000..f3fcc49f81 --- /dev/null +++ b/hw/pci-host/articia.c @@ -0,0 +1,293 @@ +/* + * Mai Logic Articia S emulation + * + * Copyright (c) 2023 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/pci/pci_device.h" +#include "hw/pci/pci_host.h" +#include "hw/irq.h" +#include "hw/i2c/bitbang_i2c.h" +#include "hw/intc/i8259.h" +#include "hw/pci-host/articia.h" + +/* + * This is a minimal emulation of this chip as used in AmigaOne board. + * Most features are missing but those are not needed by firmware and gues= ts. + */ + +OBJECT_DECLARE_SIMPLE_TYPE(ArticiaState, ARTICIA) + +OBJECT_DECLARE_SIMPLE_TYPE(ArticiaHostState, ARTICIA_PCI_HOST) +struct ArticiaHostState { + PCIDevice parent_obj; + + ArticiaState *as; +}; + +/* TYPE_ARTICIA */ + +struct ArticiaState { + PCIHostState parent_obj; + + qemu_irq irq[PCI_NUM_PINS]; + MemoryRegion io; + MemoryRegion mem; + MemoryRegion reg; + + bitbang_i2c_interface smbus; + uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out)= */ + hwaddr gpio_base; + MemoryRegion gpio_reg; +}; + +static uint64_t articia_gpio_read(void *opaque, hwaddr addr, unsigned int = size) +{ + ArticiaState *s =3D opaque; + + return (s->gpio >> (addr * 8)) & 0xff; +} + +static void articia_gpio_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + ArticiaState *s =3D opaque; + uint32_t sh =3D addr * 8; + + if (addr =3D=3D 0) { + /* in bits read only? */ + return; + } + + if ((s->gpio & (0xff << sh)) !=3D (val & 0xff) << sh) { + s->gpio &=3D ~(0xff << sh | 0xff); + s->gpio |=3D (val & 0xff) << sh; + s->gpio |=3D bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA, + s->gpio & BIT(16) ? + !!(s->gpio & BIT(8)) : 1); + if ((s->gpio & BIT(17))) { + s->gpio &=3D ~BIT(0); + s->gpio |=3D bitbang_i2c_set(&s->smbus, BITBANG_I2C_SCL, + !!(s->gpio & BIT(9))); + } + } +} + +static const MemoryRegionOps articia_gpio_ops =3D { + .read =3D articia_gpio_read, + .write =3D articia_gpio_write, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t articia_reg_read(void *opaque, hwaddr addr, unsigned int s= ize) +{ + ArticiaState *s =3D opaque; + uint64_t ret =3D UINT_MAX; + + switch (addr) { + case 0xc00cf8: + ret =3D pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(s), 0, size); + break; + case 0xe00cfc ... 0xe00cff: + ret =3D pci_host_data_le_ops.read(PCI_HOST_BRIDGE(s), addr - 0xe00= cfc, size); + break; + case 0xf00000: + ret =3D pic_read_irq(isa_pic); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%" + HWADDR_PRIx " %d\n", __func__, addr, size); + break; + } + return ret; +} + +static void articia_reg_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + ArticiaState *s =3D opaque; + + switch (addr) { + case 0xc00cf8: + pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(s), 0, val, size); + break; + case 0xe00cfc ... 0xe00cff: + pci_host_data_le_ops.write(PCI_HOST_BRIDGE(s), addr, val, size); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%" + HWADDR_PRIx " %d <- %"PRIx64"\n", __func__, addr, si= ze, val); + break; + } +} + +static const MemoryRegionOps articia_reg_ops =3D { + .read =3D articia_reg_read, + .write =3D articia_reg_write, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void articia_pcihost_set_irq(void *opaque, int n, int level) +{ + ArticiaState *s =3D opaque; + qemu_set_irq(s->irq[n], level); +} + +/* + * AmigaOne SE PCI slot to IRQ routing + * + * repository: https://source.denx.de/u-boot/custodians/u-boot-avr32.git + * refspec: v2010.06 + * file: board/MAI/AmigaOneG3SE/articiaS_pci.c + */ +static int amigaone_pcihost_bus0_map_irq(PCIDevice *pdev, int pin) +{ + int devfn_slot =3D PCI_SLOT(pdev->devfn); + + switch (devfn_slot) { + case 6: /* On board ethernet */ + return 3; + case 7: /* South bridge */ + return pin; + default: /* PCI Slot 1 Devfn slot 8, Slot 2 Devfn 9, Slot 3 Devfn 10 */ + return pci_swizzle(devfn_slot, pin); + } + +} + +static void articia_realize(DeviceState *dev, Error **errp) +{ + ArticiaState *s =3D ARTICIA(dev); + PCIHostState *h =3D PCI_HOST_BRIDGE(dev); + PCIDevice *pdev; + + bitbang_i2c_init(&s->smbus, i2c_init_bus(dev, "smbus")); + memory_region_init_io(&s->gpio_reg, OBJECT(s), &articia_gpio_ops, s, + TYPE_ARTICIA, 4); + + memory_region_init(&s->mem, OBJECT(dev), "pci-mem", UINT64_MAX); + memory_region_init(&s->io, OBJECT(dev), "pci-io", 0xc00000); + memory_region_init_io(&s->reg, OBJECT(s), &articia_reg_ops, s, + TYPE_ARTICIA, 0x1000000); + memory_region_add_subregion_overlap(&s->reg, 0, &s->io, 1); + + /* devfn_min is 8 that matches first PCI slot in AmigaOne */ + h->bus =3D pci_register_root_bus(dev, NULL, articia_pcihost_set_irq, + amigaone_pcihost_bus0_map_irq, dev, &s-= >mem, + &s->io, PCI_DEVFN(8, 0), 4, TYPE_PCI_BU= S); + pdev =3D pci_create_simple_multifunction(h->bus, PCI_DEVFN(0, 0), + TYPE_ARTICIA_PCI_HOST); + ARTICIA_PCI_HOST(pdev)->as =3D s; + pci_create_simple(h->bus, PCI_DEVFN(0, 1), TYPE_ARTICIA_PCI_BRIDGE); + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->reg); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mem); + qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq)); +} + +static void articia_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D articia_realize; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); +} + +/* TYPE_ARTICIA_PCI_HOST */ + +static void articia_pci_host_cfg_write(PCIDevice *d, uint32_t addr, + uint32_t val, int len) +{ + ArticiaState *s =3D ARTICIA_PCI_HOST(d)->as; + + pci_default_write_config(d, addr, val, len); + switch (addr) { + case 0x40: + s->gpio_base =3D val; + break; + case 0x44: + if (val !=3D 0x11) { + /* FIXME what do the bits actually mean? */ + break; + } + if (memory_region_is_mapped(&s->gpio_reg)) { + memory_region_del_subregion(&s->io, &s->gpio_reg); + } + memory_region_add_subregion(&s->io, s->gpio_base + 0x38, &s->gpio_= reg); + break; + } +} + +static void articia_pci_host_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->config_write =3D articia_pci_host_cfg_write; + k->vendor_id =3D 0x10cc; + k->device_id =3D 0x0660; + k->class_id =3D PCI_CLASS_BRIDGE_HOST; + /* + * PCI-facing part of the host bridge, + * not usable without the host-facing part + */ + dc->user_creatable =3D false; +} + +/* TYPE_ARTICIA_PCI_BRIDGE */ + +static void articia_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->vendor_id =3D 0x10cc; + k->device_id =3D 0x0661; + k->class_id =3D PCI_CLASS_BRIDGE_HOST; + /* + * PCI-facing part of the host bridge, + * not usable without the host-facing part + */ + dc->user_creatable =3D false; +} + +static const TypeInfo articia_types[] =3D { + { + .name =3D TYPE_ARTICIA, + .parent =3D TYPE_PCI_HOST_BRIDGE, + .instance_size =3D sizeof(ArticiaState), + .class_init =3D articia_class_init, + }, + { + .name =3D TYPE_ARTICIA_PCI_HOST, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(ArticiaHostState), + .class_init =3D articia_pci_host_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, + }, + { + .name =3D TYPE_ARTICIA_PCI_BRIDGE, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(PCIDevice), + .class_init =3D articia_pci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, + }, +}; + +DEFINE_TYPES(articia_types) diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index f891f026cb..de7bfb5a62 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -20,6 +20,8 @@ pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('gr= ackle.c')) pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c')) # PowerPC E500 boards pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c')) +# AmigaOne +pci_ss.add(when: 'CONFIG_ARTICIA', if_true: files('articia.c')) # Pegasos2 pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c')) =20 diff --git a/include/hw/pci-host/articia.h b/include/hw/pci-host/articia.h new file mode 100644 index 0000000000..529c240274 --- /dev/null +++ b/include/hw/pci-host/articia.h @@ -0,0 +1,17 @@ +/* + * Mai Logic Articia S emulation + * + * Copyright (c) 2023 BALATON Zoltan + * + * This work is licensed under the GNU GPL license version 2 or later. + * + */ + +#ifndef ARTICIA_H +#define ARTICIA_H + +#define TYPE_ARTICIA "articia" +#define TYPE_ARTICIA_PCI_HOST "articia-pci-host" +#define TYPE_ARTICIA_PCI_BRIDGE "articia-pci-bridge" + +#endif --=20 2.41.0