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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699367058742100001 This avoids two duplicates being presented to gdbstub. As the registers are RAZ anyway it is unlikely their value would be of use to someone using gdbstub anyway. Acked-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-Id: <20231106185112.2755262-5-alex.bennee@linaro.org> diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 79a3659c0c..cbfba532f5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -937,14 +937,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { */ { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_R, .accessfn =3D access_tdra, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, @@ -1065,9 +1065,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { /* 64 bit access versions of the (dummy) debug registers */ { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO= _GDB, + .resetvalue =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO= _GDB, + .resetvalue =3D 0 }, }; =20 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.39.2