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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id fn11-20020a056a002fcb00b006bff7c36fb3sm6367478pfb.95.2023.11.06.18.48.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 18:48:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699325340; x=1699930140; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UKokEn2/f5uDToV4b3MTyHM++CDKvKNGzEYJ6Ux0XXw=; b=jLFFeBOJ07FEmCGUbbMR0VoreCV3vw+w+2X+G2pvAuz7ix9/T9Oi5XijfGwdyMIW4h 5vsiSbfx83b7GzjkqpPIgFT0bCPiFLHkykwqwb34b4mUz07o1XvXnG52t4khPHUc6+PI //rnXDcnydJBRetEutxrz5Kv0ysAX4jJ5ivFZSdVm36aWoP4nowoTKhsRwsOzl7tZaEt yEOxijkFVi4TpPIoYV2mNuUrgXbXYp235ZTXXM4CN6fXtsID3ZU9X04HQiAedja1nUtR BsHmEw5ufCzLXbf/Z0lxdggz4S23i8PzgM6NINTeRLtEgeJIyAJm8EJFxEOVOWAalos3 gxXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699325340; x=1699930140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UKokEn2/f5uDToV4b3MTyHM++CDKvKNGzEYJ6Ux0XXw=; b=fywXfP9RvD86HxR8NYvD5mExRDf7k6UfsPlZXr9salpXM/JgS65357+gwes/3E6dz1 4HBj5EFbjQMHAhFcPcFQ+rVPS75f3FfmSkoPfDG+cokZHvQt1RCrirhJIEqboiyMMCDV OiseQB2nbuh+zA3dyHAFFGPz2SYI9+a7LrrfV6K6A7y/a16chaA79/buIRL7xcmpr3Ey a69N6ec1gRSjqTtI+4PqditwJxcQtZ0vVcA1Y06EZsDDnko7TaI1j9my1XR26k1lKM7r 8C799Ux7AJnXW6gLPHrEFKTSopKDm790gZnt4nfkKgesN+4Yn6dxOfF7SN5k2xi1Sqyn eZtg== X-Gm-Message-State: AOJu0YwnAvmneAYyDNKo6i1HaDzaFnWgqWg9abEI1BVlrK8A+Ixpc+WR bJDKtdszU5QC84EzJndyHdmyL+rFtqNgQJd77x8= X-Google-Smtp-Source: AGHT+IFFteoXLI0twyRxoo8m36QjKhP9CNYFBK1UYmwcxW53BkPxGu26N2jsMq8kt7p9WaMz5xLHUg== X-Received: by 2002:a05:6a00:1593:b0:6be:2901:2cd with SMTP id u19-20020a056a00159300b006be290102cdmr29779496pfk.10.1699325340078; Mon, 06 Nov 2023 18:49:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/35] tcg/mips: Always implement movcond Date: Mon, 6 Nov 2023 18:48:28 -0800 Message-Id: <20231107024842.7650-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231107024842.7650-1-richard.henderson@linaro.org> References: <20231107024842.7650-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1699325436270100001 Content-Type: text/plain; charset="utf-8" Expand as branch over move if not supported in the ISA. Signed-off-by: Richard Henderson Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org> --- tcg/mips/tcg-target.h | 4 ++-- tcg/mips/tcg-target.c.inc | 19 ++++++++++++++----- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c0576f66d7..0a4083f0d9 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -154,7 +154,7 @@ extern bool use_mips32r2_instructions; #endif =20 /* optional instructions detected at runtime */ -#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions @@ -169,7 +169,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 89681f00fe..82b078b9c5 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1070,13 +1070,22 @@ static void tcg_out_movcond(TCGContext *s, TCGCond = cond, TCGReg ret, if (v2 !=3D 0) { tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); } - } else { + return; + } + + /* This should be guaranteed via constraints */ + tcg_debug_assert(v2 =3D=3D ret); + + if (use_movnz_instructions) { MIPSInsn m_opc =3D eqz ? OPC_MOVZ : OPC_MOVN; - tcg_out_opc_reg(s, m_opc, ret, v1, c1); - - /* This should be guaranteed via constraints */ - tcg_debug_assert(v2 =3D=3D ret); + } else { + /* Invert the condition in order to branch over the move. */ + MIPSInsn b_opc =3D eqz ? OPC_BNE : OPC_BEQ; + tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); + tcg_out_nop(s); + /* Open-code tcg_out_mov, without the nop-move check. */ + tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); } } =20 --=20 2.34.1