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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u18-20020a170902e5d200b001cc32f46757sm6487649plf.107.2023.11.06.18.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 18:32:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699324363; x=1699929163; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6QG9uGqqG/ZxppfouZVb9w3fLYDP7x4ZVtyFJ5kQQY=; b=klByGa/MVMFtqPsxs9zgcpvz6qwQxYOxS4PI6LVVYkkWPKHFeHdGExIqVAfPM087uX NX+eUnAPgHTpJ1xp5/KC48Lw/eMJxnD7JnE6RcMQg4bkVQ1MJ5HPGVeQcWfj86aO+eo9 4zUWGC3sxOPOkUM7WpnfXGCLTOsPO15a4Ae/BHFSMEx0jdOrcGJ5bLW5rafurfMMizjl bHPOoY+HC9QCCtse6LsgMMKPDU0FLhe+vgr5D7tzfAZe+zgYknnhsMnwIdv2rd4kyVf3 cBGf7Ah6QS5coGPODvOwbA0kwaRWwmFzo09oJjhc641Y5NGj0UM3IvronPiO4mLg4lTj ZAtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699324363; x=1699929163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j6QG9uGqqG/ZxppfouZVb9w3fLYDP7x4ZVtyFJ5kQQY=; b=d8Tjhsdeq0fj9Xuw6TfRuQ2v4Wl2bw+yaOJGf2E4p+kqy0izUUq2IAc/BynlsVn67w SDsme2PZ8+6it5ztuSW3CyP2uze7TJYygd4kT2av0yfatMLJFJviDjWD0SOPRTqjoGTt SGg/bw0f8rVOaRroPFsP2WXHsKT5fLCecuzPmk6GmWFqWvOgqdXJo37ROLmtI4vpPZXi skrI1LxYyS37TGCk/yD60crvyS8F5LhTsFyQwgbvzewkGpMIwEQQ+ibICKRLR5vE9ZCu 3AuKYxf2chaSqfhofTLqJN7aQQCRv9JI05wcPUrn6MlkCkSr0k0sH+Xm2lY8kqd+RrXT S7DA== X-Gm-Message-State: AOJu0YwMEjPN6Xy6TekBeJNHq1wYF1vRFIb43uNNhGJFWCEG9Sa7Q0V2 SeCElYb16WH4RAN15UHCdzVCH+M5kakb8A== X-Google-Smtp-Source: AGHT+IFSllPW2c5d0D/LlupH7ZXZabtedpuIzVRP52MtPnQ3+zDZmUws+cWz6YrjTeRgLlhGBYqF4A== X-Received: by 2002:a17:903:11c8:b0:1cc:7ebe:4db6 with SMTP id q8-20020a17090311c800b001cc7ebe4db6mr16468755plh.39.1699324362951; Mon, 06 Nov 2023 18:32:42 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rob Bradford , Alistair Francis Subject: [PULL 48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num" Date: Tue, 7 Nov 2023 12:29:44 +1000 Message-ID: <20231107022946.1055027-49-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107022946.1055027-1-alistair.francis@wdc.com> References: <20231107022946.1055027-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699324589121100005 Content-Type: text/plain; charset="utf-8" From: Rob Bradford Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters. The "pmu-num" property now generates a warning when used by the user on the command line. Rather than storing the value for "pmu-num" convert it directly to the mask if it is specified (overwriting the default "pmu-mask" value) likewise the value is calculated from the mask if the property value is obtained. In the unusual situation that both "pmu-mask" and "pmu-num" are provided then then the order on the command line determines which takes precedence (later overwriting earlier.) Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Message-ID: <20231031154000.18134-5-rbradford@rivosinc.com> [Changes by AF - Fixup ext_zihpm logic after rebase ] Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu.c | 40 +++++++++++++++++++++++++++++++++++++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 15 +++++++------- target/riscv/tcg/tcg-cpu.c | 4 ++-- 5 files changed, 51 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 634ff673b3..f4605fb190 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -134,7 +134,7 @@ struct RISCVCPUConfig { bool ext_xtheadsync; bool ext_XVentanaCondOps; =20 - uint8_t pmu_num; + uint32_t pmu_mask; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70c0a78c6c..02db2760d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1427,8 +1427,46 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_ex= ts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint8_t pmu_num; + + visit_type_uint8(v, name, &pmu_num, errp); + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; + } + + if (pmu_num =3D=3D 0) { + cpu->cfg.pmu_mask =3D 0; + } else { + cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, pmu_num); + } + + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); +} + +static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint8_t pmu_num =3D ctpop32(cpu->cfg.pmu_mask); + + visit_type_uint8(v, name, &pmu_num, errp); +} + +const PropertyInfo prop_pmu_num =3D { + .name =3D "pmu-num", + .get =3D prop_pmu_num_get, + .set =3D prop_pmu_num_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK= (3, 16)), + {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 14bb2d7819..fdde243e04 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -316,7 +316,7 @@ static bool pmu_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.pmu_num; + return (cpu->cfg.pmu_mask > 0); } =20 static const VMStateDescription vmstate_pmu_ctr_state =3D { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..0e7d58b8a5 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -18,14 +18,13 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" #include "sysemu/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) =20 /* * To keep it simple, any event can be mapped to any programmable counters= in @@ -184,7 +183,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_ev= ent_idx event_idx) CPURISCVState *env =3D &cpu->env; gpointer value; =20 - if (!cpu->cfg.pmu_num) { + if (!cpu->cfg.pmu_mask) { return 0; } value =3D g_hash_table_lookup(cpu->pmu_event_ctr_map, @@ -432,9 +431,12 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t= value, uint32_t ctr_idx) =20 void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - uint8_t pmu_num =3D cpu->cfg.pmu_num; + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); + return; + } =20 - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } @@ -445,6 +447,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } =20 - /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, pmu_num); + cpu->pmu_avail_ctrs =3D cpu->cfg.pmu_mask; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 144bdac1b2..08adad304d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -600,7 +600,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } =20 if (!cpu->cfg.ext_zihpm) { - cpu->cfg.pmu_num =3D 0; + cpu->cfg.pmu_mask =3D 0; cpu->pmu_avail_ctrs =3D 0; } =20 @@ -688,7 +688,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) riscv_timer_init(cpu); } =20 - if (cpu->cfg.pmu_num) { + if (cpu->cfg.pmu_mask) { riscv_pmu_init(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.41.0