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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699324589129100006 Content-Type: text/plain; charset="utf-8" From: Max Chou This patch adds following v1.0.0 ratified vector crypto extensions support to the RISC-V disassembler. - Zvbb - Zvbc - Zvkb - Zvkg - Zvkned - Zvknha - Zvknhb - Zvksed - Zvksh Signed-off-by: Max Chou Message-ID: <20231026151828.754279-14-max.chou@sifive.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index ec33e447f5..7ea6ea050e 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -862,6 +862,47 @@ typedef enum { rv_op_fltq_q =3D 831, rv_op_fleq_h =3D 832, rv_op_fltq_h =3D 833, + rv_op_vaesdf_vv =3D 834, + rv_op_vaesdf_vs =3D 835, + rv_op_vaesdm_vv =3D 836, + rv_op_vaesdm_vs =3D 837, + rv_op_vaesef_vv =3D 838, + rv_op_vaesef_vs =3D 839, + rv_op_vaesem_vv =3D 840, + rv_op_vaesem_vs =3D 841, + rv_op_vaeskf1_vi =3D 842, + rv_op_vaeskf2_vi =3D 843, + rv_op_vaesz_vs =3D 844, + rv_op_vandn_vv =3D 845, + rv_op_vandn_vx =3D 846, + rv_op_vbrev_v =3D 847, + rv_op_vbrev8_v =3D 848, + rv_op_vclmul_vv =3D 849, + rv_op_vclmul_vx =3D 850, + rv_op_vclmulh_vv =3D 851, + rv_op_vclmulh_vx =3D 852, + rv_op_vclz_v =3D 853, + rv_op_vcpop_v =3D 854, + rv_op_vctz_v =3D 855, + rv_op_vghsh_vv =3D 856, + rv_op_vgmul_vv =3D 857, + rv_op_vrev8_v =3D 858, + rv_op_vrol_vv =3D 859, + rv_op_vrol_vx =3D 860, + rv_op_vror_vv =3D 861, + rv_op_vror_vx =3D 862, + rv_op_vror_vi =3D 863, + rv_op_vsha2ch_vv =3D 864, + rv_op_vsha2cl_vv =3D 865, + rv_op_vsha2ms_vv =3D 866, + rv_op_vsm3c_vi =3D 867, + rv_op_vsm3me_vv =3D 868, + rv_op_vsm4k_vi =3D 869, + rv_op_vsm4r_vv =3D 870, + rv_op_vsm4r_vs =3D 871, + rv_op_vwsll_vv =3D 872, + rv_op_vwsll_vx =3D 873, + rv_op_vwsll_vi =3D 874, } rv_op; =20 /* register names */ @@ -2008,6 +2049,47 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, + { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -3176,6 +3258,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 0: switch ((inst >> 26) & 0b111111) { case 0: op =3D rv_op_vadd_vv; break; + case 1: op =3D rv_op_vandn_vv; break; case 2: op =3D rv_op_vsub_vv; break; case 4: op =3D rv_op_vminu_vv; break; case 5: op =3D rv_op_vmin_vv; break; @@ -3198,6 +3281,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) } break; case 19: op =3D rv_op_vmsbc_vvm; break; + case 20: op =3D rv_op_vror_vv; break; + case 21: op =3D rv_op_vrol_vv; break; case 23: if (((inst >> 20) & 0b111111) =3D=3D 32) op =3D rv_op_vmv_v_v; @@ -3226,6 +3311,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 47: op =3D rv_op_vnclip_wv; break; case 48: op =3D rv_op_vwredsumu_vs; break; case 49: op =3D rv_op_vwredsum_vs; break; + case 53: op =3D rv_op_vwsll_vv; break; } break; case 1: @@ -3323,6 +3409,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 9: op =3D rv_op_vaadd_vv; break; case 10: op =3D rv_op_vasubu_vv; break; case 11: op =3D rv_op_vasub_vv; break; + case 12: op =3D rv_op_vclmul_vv; break; + case 13: op =3D rv_op_vclmulh_vv; break; case 16: switch ((inst >> 15) & 0b11111) { case 0: if ((inst >> 25) & 1) op =3D rv_op_vmv_x_s; br= eak; @@ -3338,6 +3426,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 5: op =3D rv_op_vsext_vf4; break; case 6: op =3D rv_op_vzext_vf2; break; case 7: op =3D rv_op_vsext_vf2; break; + case 8: op =3D rv_op_vbrev8_v; break; + case 9: op =3D rv_op_vrev8_v; break; + case 10: op =3D rv_op_vbrev_v; break; + case 12: op =3D rv_op_vclz_v; break; + case 13: op =3D rv_op_vctz_v; break; + case 14: op =3D rv_op_vcpop_v; break; } break; case 20: @@ -3406,6 +3500,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) } break; case 17: op =3D rv_op_vmadc_vim; break; + case 20: case 21: op =3D rv_op_vror_vi; break; case 23: if (((inst >> 20) & 0b111111) =3D=3D 32) op =3D rv_op_vmv_v_i; @@ -3437,11 +3532,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) case 45: op =3D rv_op_vnsra_wi; break; case 46: op =3D rv_op_vnclipu_wi; break; case 47: op =3D rv_op_vnclip_wi; break; + case 53: op =3D rv_op_vwsll_vi; break; } break; case 4: switch ((inst >> 26) & 0b111111) { case 0: op =3D rv_op_vadd_vx; break; + case 1: op =3D rv_op_vandn_vx; break; case 2: op =3D rv_op_vsub_vx; break; case 3: op =3D rv_op_vrsub_vx; break; case 4: op =3D rv_op_vminu_vx; break; @@ -3466,6 +3563,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) } break; case 19: op =3D rv_op_vmsbc_vxm; break; + case 20: op =3D rv_op_vror_vx; break; + case 21: op =3D rv_op_vrol_vx; break; case 23: if (((inst >> 20) & 0b111111) =3D=3D 32) op =3D rv_op_vmv_v_x; @@ -3494,6 +3593,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 45: op =3D rv_op_vnsra_wx; break; case 46: op =3D rv_op_vnclipu_wx; break; case 47: op =3D rv_op_vnclip_wx; break; + case 53: op =3D rv_op_vwsll_vx; break; } break; case 5: @@ -3554,6 +3654,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 9: op =3D rv_op_vaadd_vx; break; case 10: op =3D rv_op_vasubu_vx; break; case 11: op =3D rv_op_vasub_vx; break; + case 12: op =3D rv_op_vclmul_vx; break; + case 13: op =3D rv_op_vclmulh_vx; break; case 14: op =3D rv_op_vslide1up_vx; break; case 15: op =3D rv_op_vslide1down_vx; break; case 16: @@ -3686,6 +3788,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 7: op =3D rv_op_csrrci; break; } break; + case 29: + if (((inst >> 25) & 1) =3D=3D 1 && ((inst >> 12) & 0b111) =3D= =3D 2) { + switch ((inst >> 26) & 0b111111) { + case 32: op =3D rv_op_vsm3me_vv; break; + case 33: op =3D rv_op_vsm4k_vi; break; + case 34: op =3D rv_op_vaeskf1_vi; break; + case 40: + switch ((inst >> 15) & 0b11111) { + case 0: op =3D rv_op_vaesdm_vv; break; + case 1: op =3D rv_op_vaesdf_vv; break; + case 2: op =3D rv_op_vaesem_vv; break; + case 3: op =3D rv_op_vaesef_vv; break; + case 16: op =3D rv_op_vsm4r_vv; break; + case 17: op =3D rv_op_vgmul_vv; break; + } + break; + case 41: + switch ((inst >> 15) & 0b11111) { + case 0: op =3D rv_op_vaesdm_vs; break; + case 1: op =3D rv_op_vaesdf_vs; break; + case 2: op =3D rv_op_vaesem_vs; break; + case 3: op =3D rv_op_vaesef_vs; break; + case 7: op =3D rv_op_vaesz_vs; break; + case 16: op =3D rv_op_vsm4r_vs; break; + } + break; + case 42: op =3D rv_op_vaeskf2_vi; break; + case 43: op =3D rv_op_vsm3c_vi; break; + case 44: op =3D rv_op_vghsh_vv; break; + case 45: op =3D rv_op_vsha2ms_vv; break; + case 46: op =3D rv_op_vsha2ch_vv; break; + case 47: op =3D rv_op_vsha2cl_vv; break; + } + } + break; case 30: switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { --=20 2.41.0