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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u18-20020a170902e5d200b001cc32f46757sm6487649plf.107.2023.11.06.18.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 18:29:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699324199; x=1699928999; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SBHdtGkhdIsTynNenPpt3LElifNcd19zbMZr8mYJw3I=; b=HtwwlOZgTLzCWbGJd52DJEDGELKCWXxRdEok2r+HYF9CQmDO61WN/QY8d6YsSJTRGz 43GwokbpwuYu/z/Q2ON/ZmK2CQWqDf6fab4LVfOonpgVLcwULwUzXfPgWi4BiYCXxl6c 397Bi8btLPMLdTuiZ80DCp/MyoDhHJb+2d8ntXFTnqQzUO4pg2UCt7gT66woOFsvWcKG Ut9OxtNkvXklSghomVi4tTIkw4S8TsVws/opZbVuo/wocvyHfuV1TRKix+T0KCo7C2V8 eaO1PpQMzBEaPwndav0NRjuBuXIHmsjFuSHqQBF0/DrEkWcJiU3Oj9kbf7WhgwFihGDN jXAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699324199; x=1699928999; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SBHdtGkhdIsTynNenPpt3LElifNcd19zbMZr8mYJw3I=; b=f8t1jIic1rE0jTMFLZaB566VWRjcFZGvrS8ZwnXgraMIIPXidKlgGN6FoxRTR+J4cG I8AXbJGn1ctNAaMCkUdBt3IZcgOWLRXeH6s/BDh7rTOg0KNpcRCWqF2G+TGjKD9IzDKe 2uR3zTkB89l3/9aLVKODOMNJZOB9ajNuKHUN0jWjZrffuQ6G8XWAkX4dxf0LM7fQQ0du bBIEyVqLZ2AewcI/ssasBqXsx6fZpbnR5eq/NPYuSF5B5ZBj3zhDgMSYy4D/L0Dnt3ut GgRP2tdHghT4QOHZhoTEsZqWHP62wdy25V+tGBO6XnJsxaQ8P7jQk2OPd2NswzkfYbI3 9lXg== X-Gm-Message-State: AOJu0YyrsjhMlHMkBwP15fDqC7ZtugNC/j4KQaqjgxwJgK/Bofz9vWf5 KWDPEE9aXiK+xO3cL666tL5hvYaa3YSLlA== X-Google-Smtp-Source: AGHT+IEO8PwcZ1FAMo03JGydC39FLqQX0rUjbbEeGq7IwA7Pe4vwL+TWbrrYPqbmu5Lc6G/Gv1bVtA== X-Received: by 2002:a17:90a:ce8b:b0:27d:7887:ddc5 with SMTP id g11-20020a17090ace8b00b0027d7887ddc5mr24277465pju.32.1699324199246; Mon, 06 Nov 2023 18:29:59 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 01/49] target/riscv: rename ext_ifencei to ext_zifencei Date: Tue, 7 Nov 2023 12:28:57 +1000 Message-ID: <20231107022946.1055027-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231107022946.1055027-1-alistair.francis@wdc.com> References: <20231107022946.1055027-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1699324264267100006 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add a leading 'z' to improve grepping. When one wants to search for uses of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i ifencei'. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20231012164604.398496-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu.c | 22 +++++++++++----------- target/riscv/tcg/tcg-cpu.c | 8 ++++---- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..a3f96eb878 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -61,7 +61,7 @@ struct RISCVCPUConfig { bool ext_zksed; bool ext_zksh; bool ext_zkt; - bool ext_ifencei; + bool ext_zifencei; bool ext_icsr; bool ext_icbom; bool ext_icboz; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..3693eabb34 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -80,7 +80,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), - ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei), ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), @@ -382,7 +382,7 @@ static void riscv_any_cpu_init(Object *obj) env->priv_ver =3D PRIV_VERSION_LATEST; =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; @@ -430,7 +430,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) #endif =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; @@ -448,7 +448,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) #endif =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; } @@ -494,7 +494,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) =20 /* Enable ISA extensions */ cpu->cfg.mmu =3D true; - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; cpu->cfg.ext_icbom =3D true; @@ -566,7 +566,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) #endif =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; @@ -584,7 +584,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) #endif =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; } @@ -602,7 +602,7 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.epmp =3D true; =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; } @@ -619,7 +619,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) #endif =20 /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; } @@ -1242,7 +1242,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), - MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true), + MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), @@ -1347,7 +1347,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { =20 /* Deprecated entries marked for future removal */ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] =3D { - MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), + MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true), MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a28918ab30..9b8f3f54a7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -278,7 +278,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) { =20 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && !cpu->cfg.ext_icsr) { @@ -286,15 +286,15 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) return; } =20 - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && - !cpu->cfg.ext_ifencei) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) && + !cpu->cfg.ext_zifencei) { error_setg(errp, "RVG requires Zifencei but user set " "Zifencei to false"); return; } =20 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true); =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 25cb60558a..faf6d65064 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -799,7 +799,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a) =20 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { - if (!ctx->cfg_ptr->ext_ifencei) { + if (!ctx->cfg_ptr->ext_zifencei) { return false; } =20 --=20 2.41.0